PPM-C412/Power-on Self-Test (POST) Codes
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Appendix C. Power-on Self-Test (POST) Codes
If the system hangs before the BIOS can process the error, the value displayed at the
I/O port address 80h is the code of the last successful operation. In this case, the screen
does not display an error code.
POST Codes
POST Codes are 8-bit unsigned integer values that are sent to a specific I/O port (where
hardware can decode and display the value) or to the DDT debugger.
The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot
process. The following table describes the type of checkpoints that can occur during the
POST portion of the BIOS3.
Checkpoints may differ between different platforms based on system configuration.
Checkpoints may change due to vendor requirements, system chipset, or option ROMs
from add-in PCI devices.
Table 22:
POST code checkpoints
Checkpoint
Description
03
Disables NMI, parity, video for EGA, and DMA controllers. Initializes BIOS, POST, runtime data area.
Also initializes BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the
kernel variable
wCMOSFlags
.
04
Checks CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verifies
CMOS checksum manually by reading storage area. If the CMOS checksum is bad, updates CMOS with
power-on default values and clear passwords. Initializes status register A.
Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible
PICs in the system.
05
Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06
Performs R/W test to CH-2 count reg. Initializes CH-0 as system timer. Install the POSTINT1Ch
handler. Enables IRQ-0 in PIC for system timer interrupt.
Traps INT1Ch vector to
POSTINT1ChHandlerBlock
.
07
Fixes CPU POST interface calling pointer.
08
Initializes the CPU. The BAT test is being done on KBC. Programming the keyboard controller
command byte is done after Auto detection of KB/MS using AMI KB-5.
C0
Early CPU Init Start – Disable Cache – Init Local APIC
C1
Sets up boot strap processor information.
C2
Sets up boot strap processor for POST.
C5
Enumerates and sets up application processors.
C6
Re-enables cache for boot strap processor.
C7
Early CPU Init Exit
0A
Initializes the 8042 compatible keyboard controller.
0B
Detects the presence of PS/2 mouse.
