PPM-C412/Configuration
v1.0
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Page 22
7.8.4 POL0 through POL2
These registers are accessible when Page 1 is selected. They allow interrupt polarity
selection on a port-by-port and bit-by-bit basis. Writing a 1 to a bit position selects the
rising edge detection interrupts. Writing a 0 to a bit position selects falling edge
detection interrupts.
7.8.5 ENAB0 through ENAB2
These registers are accessible when Page 2 is selected. They allow for port-by-port and
bit-by-bit enabling of the edge detection interrupts. When set to a 1, the edge detection
interrupt is enabled for the corresponding port and bit. When cleared to 0, the bit’s edge
detection interrupt is disabled. Note that this register can be used to individually clear a
pending interrupt by disabling and re-enabling the pending interrupt.
7.8.6 INT_ID0 through INT_ID2
These registers are accessible when Page 3 is selected. They are used to identify
currently pending edge interrupts. A bit, when read as a 1, indicates that an edge of the
polarity programmed into the corresponding polarity register has been recognized. Note
that a write to this register (value ignored) clears ALL the pending interrupts in this
register.
7.9 Watchdog Timer
The PPM-C412 features an advanced watchdog timer that can be used to guard against
software lockups. Three interfaces are provided to the watchdog timer. The Advanced
interface is the most flexible and recommended for new designs. The other two
interface options are provided for software compatibility with older WinSystems
single-board computers.
7.9.1 Advanced
Enable the watchdog timer in the BIOS Settings by entering a value for Watch-Dog
Timeout on the Peripherals screen. Any non-zero value represents the number of
minutes prior to reset during system boot. When the operating system is loaded,
disable or reconfigure the watchdog in the application software.
Table 12:
Page bits
Page
D7
D6
D5-D0
Page 0
0
0
1/0
Page 1
0
1
1/0
Page 2
1
0
1/0
Page 3
1
1
1/0
