WinSystems PPM-C407, Руководство по эксплуатации продукта

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PPM-C407/Configuration
v1.0 www.winsystems.com Page 14
7.4.3 PAGE/LOCK
This register serves two purposes. The upper two bits (D6 and D7) select the register
page in use. Bits 0-5 allow for locking the I/O ports. Write a 1 to the I/O port position to
prohibit further writes to the corresponding I/O port:
7.4.4 POL0 through POL2
These registers are accessible when Page 1 is selected. They allow interrupt polarity
selection on a port-by-port and bit-by-bit basis. Writing a 1 to a bit position selects the
rising edge detection interrupts while writing a 0 to a bit position selects falling edge
detection interrupts.
7.4.5 ENAB0 through ENAB2
These registers are accessible when Page 2 is selected. They allow for port-by-port and
bit-by-bit enabling of the edge detection interrupts. When set to a 1, the edge detection
interrupt is enabled for the corresponding port and bit. When cleared to 0, the bit’s edge
detection interrupt is disabled. Note that this register can be used to individually clear a
pending interrupt by disabling and re-enabling the pending interrupt.
7.4.6 INT_ID0 through INT_ID2
These registers are accessible when Page 3 is selected. They are used to identify
currently pending edge interrupts. A bit when read as a 1 indicates that an edge of the
polarity programmed into the corresponding polarity register has been recognized. Note
that a write to this register (value ignored) clears ALL of the pending interrupts in this
register.
Page D7 D6 D5-D0
Page 0 0 0 1/0
Page 1 0 1 1/0
Page 2 1 0 1/0
Page 3 1 1 1/0
PRELIMINARY