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140721 

     PRODUCT 

MANUAL 

PCM-MIO-G-1    19

7

6

5

4

3

2

1

0

DATA_LO

12

R/W

LOW ORDER DATA BYTE

DATA-BIT 7

DATA-BIT 6

DATA-BIT 5

DATA-BIT 4

DATA-BIT 3

DATA-BIT 2

DATA-BIT 1

DATA-BIT 0

READBACK 

(1)

12

R

LOW ORDER DATA BYTE

DATA-BIT 7

DATA-BIT 6

DATA-BIT 5

DATA-BIT 4

DATA-BIT 3

DATA-BIT 2

DATA-BIT 1

DATA-BIT 0

DATA_HI

13

R/W

HIGH ORDER DATA BYTE

DATA-BIT 15

DATA-BIT 14

DATA-BIT 13

DATA-BIT 12

DATA-BIT 11

DATA-BIT 10

DATA-BIT 9

DATA-BIT 8

READBACK 

(1)

13

R

HIGH ORDER DATA BYTE

DATA-BIT 15

DATA-BIT 14

DATA-BIT 13

DATA-BIT 12

DATA-BIT 11

DATA-BIT 10

DATA-BIT 9

DATA-BIT 8

COMMAND 

(2)

14

R/W

COMMAND

CMD-BIT 7

CMD-BIT 6

CMD-BIT 5

CMD-BIT 4

CMD-BIT 3

CMD-BIT 2

CMD-BIT 1

CMD-BIT 0

RESOURCE 

(3) 

14

R/W

DMA CHANNEL ASSIGNMENT

INTERRUPT ROUTING ASSIGNMENT 

IRQ[15-3] 0, 1, 2, 8 AND 13 NOT AVAILABLE

DATA

REGISTER

BIT 1

DATA

REGISTER

BIT 0

DATA

REGISTER

BIT 1

DATA

REGISTER

BIT 0

BIT 3

BIT 2

BIT 1

BIT 0

RESOURCE 

ENABLE

15

W

X

X

D/A2 SELECT

READBACK 

ENABLE

REGISTER 

SELECT

DATA DRQ

ENABLE (4)

CMD DRQ

ENABLE (4)

INTERRUPT

ENABLE (4) 

STATUS 

(5) 

15

R

DATA READY

DATA DMA

REQUEST

PENDING (4)

CMD DMA

REQUEST

PENDING (4)

INTERRUPT

REQUEST

PENDING (4)

REGISTER

SELECT

STATUS

DATA DRQ

ENABLE

STATUS (4)

CMD DRQ

ENABLE

STATUS (4)

INTERRUPT 

EANBLE BIT 

STATUS (4)

IRQ 

REGISTER 

(6)

15

R

DATA READY

DATA DMA 

REQUEST 

PENDING (4)

CMD DMA 

REQUEST 

PENDING (4)

DA2 IRQ 

PENDING 

DIO IRQ 

PENDING

DA/1 IRQ 

PENDING

AD/2 IRQ 

PENDING

AD/1 IRQ 

PENDING

Address (Base+)

Read/Write

Register

Notes:   (1)  Accessed when READBACK ENABLE (BASE +15 bit 4) = 1
 

(2)  Accessed when REGISTER SELECT (BASE +15 bit 3) = 0

 

(3)  Accessed when REGISTER SELECT (BASE +15 bit 3) = 1

 

(4)  0=Disabled, 1=Enable

D/A2 - Starting at BASE +12

As shown in the table below, interface to the 2nd device is almost identical to the first with a change in the base address.  
The RESOURCE ENABLE register does contain an additional register select bit, MASTER IRQ / DA2 SELECT.  If this bit 

is set to 1, reading BASE +15 will result in the status of the Master Interrupt Status Register.

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Содержание PCM-MIO-G-1

Страница 1: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

Страница 2: ...gton TX 76011 http www winsystems com PCM MIO G 1 16 Channel 16 bit Analog Inputs 8 Channel 12 bit Analog Outputs and 48 Digital I O PRODUCT MANUAL Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Страница 3: ...RODUCT MANUAL PCM MIO G 1 2 P N 400 0338 000 Date Code ECO Number 060103 Preliminary 161025 A 140721 REVISION HISTORY Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Страница 4: ...Address 8 Analog Input ADC 9 J2 ADC Analog Input Connections 9 Analog Output DAC 10 J1 J3 DAC Analog Output Connections 10 Digital I O Interface 11 J8 J9 Digital I O 11 J10 VCC Enable 11 PC 104 BUS Interface 12 J5 J6 PC 104 12 SOFTWARE SUMMARY 13 A D Converters 13 D A Converters 18 Registers 24 Register Definitions WS16C48 24 Register Details 24 MECHANICAL DRAWING 27 WARRANTY INFORMATION 28 Artisa...

Страница 5: ...n 1 and is also highlighted with a square where applicable J7 DEFAULT BASE I O ADDRESS J5 PC 104 CONNECTOR J10 DIGITAL I O VCC ENABLED J8 DIGITAL I O J1 ANALOG OUTPUT J3 ANALOG OUTPUT J9 DIGITAL I O J6 PC 104 CONNECTOR J2 ANALOG INPUT CONNECTIONS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Страница 6: ... REFERENCE DIGITAL I O J10 VCC Enable Visual Index J7 Base I O Address Visual Index BASE I O SELECTION NOTE Jumper Part numbers W S G201 0002 005 and SAMTEC 2SN BK G are applicable to all jumpers These are available in a five piece kit from WinSystems Part KIT JMP G 200 5V is provided at pin 49 of J9 3 4 5V is provided at pin 49 of J8 1 2 No Power at Pin 49 of J8 J9 default OPEN 3 4 J10 1 2 Artisa...

Страница 7: ...2 bit Digital to Analog D A LTC 2704CGW 12 Output ranges 0 5V 0 10V 5V or 10V 2 5V 2 5V to 7 5V Each channel independently programmable for output type and range Output channels can be updated and cleared individually or simultaneously Interrupt I O supported Supports industry standard signal conditioners Digital I O 48 bidirectional lines with Input Output or Output with Readback WS16C48 12 mA si...

Страница 8: ...s in the system The specific device locations and register offsets are discussed in more detail in the Software Summary section Base I O Address Analog To Digital The PCM MIO analog to digital conversion inputs are implemented by using two 16 bit Linear Technologies LTC 1859CG devices The board supports up to 16 single ended input channels 8 differential input channels or various combinations of b...

Страница 9: ...ce locations and register offsets are discussed in more detail in the Software Summary section J7 Base I O Address Visual Index CONNECTOR REFERENCE Example 300HEX Default 0 0 0 0 0 0 1 1 0 0 0 X X X X X A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Jumper OPEN 1 Jumper INSTALLED 0 1 3 5 7 9 11 13 15 17 19 21 J7 2 4 6 8 10 12 14 16 18 20 22 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Artisan Tec...

Страница 10: ... desired input range 0V to 5V 0V to 10V 5V and 10V The LTC 1859CG uses a successive approximation algorithm and an internal sample and hold circuit to convert an analog input signal to 16 bit digital data The output is two s complement binary for bipolar mode and offset binary for unipolar mode Programming information for the A D controller is provided in the Software Summary section of this manua...

Страница 11: ...h specific voltage ranges on a per channel basis Each of the 8 channels can be programmed to any one of the six output ranges 0V to 5V 0V to 10V 2 5V 5V 10V and 2 5V to 7 5V Programming information for the D A controller is provided in the Software Summary section of this manual The Analog Output channels are terminated at J1 and J3 The pin definitions are shown in the illustration above GND GND G...

Страница 12: ... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND J8 J9 Digital I O Visual Index PCB Connector TEKA SVC225B3580135 0 J8 TEKA SRC225C425M126 0 J9 Mating Connector ITW PANCON 050 050 455A Digital I O Connectors The 48 lines of parallel I O are terminated through two 50 pin connectors at J8 and J9 The J9 connector handles I O ports 0 2 while J8 handl...

Страница 13: ... C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 GND MEMCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 5V MASTER GND GND GND SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR MEMW SD8 SB9 SD10 SD11 SD12 SD13 SD14 SD15 KEY J6 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 B1 B2 B3 B4 ...

Страница 14: ...ATA DMA REQUEST PENDING 3 CMD DMA REQUEST PENDING 3 INTERRUPT REQUEST PENDING 3 REGISTER SELECT STATUS DATA DRQ ENABLE STATUS 3 CMD DRQ ENABLE STATUS 3 INTERRUPT EANBLE BIT STATUS 3 A d d r e s s B a s e R e a d W r i t e R e g i s t e r A D Converters The PCM MIO uses two Linear Tech LTC 1859CG 8 channel A D converters Each device is independently software configurable to support the listed input...

Страница 15: ...ESOURCE ENABLE 7 W X X X X REGISTER SELECT DATA DRQ ENABLE 3 CMD DRQ ENABLE 3 INTERRUPT ENABLE 3 STATUS 7 R DATA READY DATA DMA REQUEST PENDING 3 CMD DMA REQUEST PENDING 3 INTERRUPT REQUEST PENDING 3 REGISTER SELECT STATUS DATA DRQ ENABLE STATUS 3 CMD DRQ ENABLE STATUS 3 INTERRUPT EANBLE BIT STATUS 3 A d d r e s s B a s e R e a d W r i t e R e g i s t e r A D2 Starting at BASE 4 The interface for ...

Страница 16: ...e measured with respect to GND Both the and inputs are sampled simultaneously so commode mode noise in rejected Range Selection Bits 3 and 2 of the command register determine the input range for the conversion Setting UNI to a logical one selects a unipolar conversion while a zero selects bipolar The GAIN bit selects the input span for the conversion in conjuntion with the UNI bit The table below ...

Страница 17: ... 0 1 2 3 4 5 6 7 COM 8 Single Ended CHANNEL 0 1 2 3 4 5 6 7 COM Combinations of Differential and Single Ended CHANNEL 4 5 6 7 COM UNUSED 1st Conversion CHANNEL 4 5 6 7 COM 2nd Conversion Changing the MUX Assignment On The Fly Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Страница 18: ...Hi_Byte The data received is actually the result of the first CMD written Realize that all readings will be offset by one action due to the latching of the serial input mechanism 8 Additional readings are achieved by repeating steps 5 through 7 Please read the documentation included with the sample programs and drivers for more complex examples A D Interrupts To operate using interrupt mode IRQ ro...

Страница 19: ...E 3 10 R W DMA CHANNEL ASSIGNMENT INTERRUPT ROUTING ASSIGNMENT IRQ 15 3 0 1 2 8 AND 13 NOT AVAILABLE DATA REGISTER BIT 1 DATA REGISTER BIT 0 DATA REGISTER BIT 1 DATA REGISTER BIT 0 BIT 3 BIT 2 BIT 1 BIT 0 RESOURCE ENABLE 11 W X X X READBACK ENABLE REGISTER SELECT DATA DRQ ENABLE 4 CMD DRQ ENABLE 4 INTERRUPT ENABLE 4 STATUS 11 R DATA READY DATA DMA REQUEST PENDING 4 CMD DMA REQUEST PENDING 4 INTERR...

Страница 20: ... ENABLE REGISTER SELECT DATA DRQ ENABLE 4 CMD DRQ ENABLE 4 INTERRUPT ENABLE 4 STATUS 5 15 R DATA READY DATA DMA REQUEST PENDING 4 CMD DMA REQUEST PENDING 4 INTERRUPT REQUEST PENDING 4 REGISTER SELECT STATUS DATA DRQ ENABLE STATUS 4 CMD DRQ ENABLE STATUS 4 INTERRUPT EANBLE BIT STATUS 4 IRQ REGISTER 6 15 R DATA READY DATA DMA REQUEST PENDING 4 CMD DMA REQUEST PENDING 4 DA2 IRQ PENDING DIO IRQ PENDIN...

Страница 21: ...mmand word consists of a 4 bit command and a 4 bit address as shown 7 6 5 4 3 2 1 0 C3 C2 C1 C0 A3 A2 A1 A0 C3 C2 C1 C0 COMMAND Readback Point Current Input Word Readback Pointer Next Input Word 0 0 1 0 Write to B1 Span DAC n Set by Previous Command B1 Span DAC n 0 0 1 1 Write to B1 Span DAC n Set by Previous Command B1 Code DAC n 0 1 0 0 Update B1 B2 DAC n Set by Previous Command B2 Span DAC n 0 ...

Страница 22: ... as shown in the Command Codes Table The Readback Enable bit must be set to 1 to read this data Note If the Readback Enable bit is set to 0 a read of the DAC data registers will return the last value written to that register not the Readback value of the actual buffers A3 A2 A1 A0 n Readback Pointer n 0 0 0 0 DAC A DAC A 0 0 1 0 DAC B DAC B 0 1 0 0 DAC C DAC C 0 1 1 0 DAC D DAC D 1 1 1 1 All DACs ...

Страница 23: ...ster Interrupt Status Register DMA Support DMA operation is available for this device A sample of these operations under DOS is provided on website These operations under other operating systems can be quite complex and are beyond the scope of this manual D A Examples The most basic method is to first set the output span for a channel and then write the output value for that channel Notice that th...

Страница 24: ...0 to BASE 10 Move data to B1 Span 5 To set Span Configuration for Channel 3 Write Span Configuration data 00000011 to BASE 8 Set Span 10V to 10V Write 00000000 zero to BASE 9 High Order Data Byte Write CMD 00100110 to BASE 10 Move data to B1 Span 6 To pre load Data Output for Channel 0 Write Low Byte data to BASE 8 Write High Byte data to BASE 9 Write CMD 00110000 to BASE 10 Move data to B1 Code 7...

Страница 25: ...ch of the six ports can be individually programmed for input or output Writing a 0 to a bit position causes the corresponding output pin to go to a high impedance state pulled high by external 10 KΩ resistors This allows it to be used as an input When used in the input mode a read reflects the inverted state of the I O pin such that a high on the pin will read as a 0 in the register Writing a 1 to...

Страница 26: ...ing edge detection interrupts ENAB0 ENAB2 These registers are accessible when Page 2 is selected They allow for port by port and bit by bit enabling of the edge detection interrupts When set to a 1 the edge detection interrupt is enabled for the corresponding port and bit When cleared to 0 the bit s edge detection interrupt is disabled Note that this register can be used to individually clear a pe...

Страница 27: ...the limited number of interrupts available this register is very helpful by allowing your application to share a single interrupt amongst all the on board devices The register is accessible by properly selecting BIT 5 at BASE 15 When BIT 5 is set to 1 the register at BASE 15 can be read as follows X X X D A2 DIO D A1 A D2 A D1 Interrupt Pending Artisan Technology Group Quality Instrumentation Guar...

Страница 28: ...140721 PRODUCT MANUAL PCM MIO G 1 27 MECHANICAL DRAWING Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Страница 29: ...eafter delivered to Customer within the United States All fees and costs for shipment outside of the United States shall be paid by Customer The foregoing warranty shall not apply to any Products of Software which have been subject to abuse misuse vandalism accidents alteration neglect unauthorized repair or improper installations THERE ARE NO WARRANTIES BY WINSYSTEMS EXCEPT AS STATED HEREIN THERE...

Страница 30: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

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