EBC-C413/Configuration
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7.4.6 INT_ID0 through INT_ID2
These registers are accessible when Page 3 is selected. They are used to
identify currently pending edge interrupts. A bit when read as a
1
indicates
that an edge of the polarity programmed into the corresponding polarity
register has been recognized. A write to this register (value ignored) clears
ALL of the pending interrupts in this register.
7.5
Watchdog Timer
The EBC-C413 features an advanced watchdog timer that can be used to
guard against software lockups.
7.5.1 Enable and Set the Timer
The watchdog timer can be enabled in the BIOS Settings by entering a
value for
Watchdog Timeout
on the
Advanced/SIO
>
FPGA G639
screen.
Any non-zero value represents the number of minutes prior to reset
during system boot. When the operating system is loaded, the watchdog
can be disabled or reconfigured in the application software.
NOTE Use a longer reset interval if the watchdog is enabled and the operating
system restarts.
The watchdog can also be enabled, disabled, or reset by writing the
appropriate values to the configuration registers located at I/O addresses
565h and 566h. To enable the watchdog, write a timeout value other than
zero to 566h. To disable the watchdog, write a zero (00h) to 566h. The
watchdog timer is serviced by writing the desired timeout value to I/O port
566h. If the watchdog has not been serviced within the allotted time, the
circuit resets the CPU.
The timeout value (specified by I/O address 566h) can be set from 1 to 255
and specified in seconds or minutes through I/O address 565h. Set bit 7 of
address 565h to
1
for seconds, and clear to
0
for minutes. See the
following table for examples.