EBC-C413/Configuration
v1.2
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Page 15
7.2
I/O Port Map
The EBC-C413 uses plug-and-play (PnP) BIOS resource allocation. Take
care to avoid contention with resources allocated by the BIOS.
The EBC-C413 utilizes a Low Pin Count to Industry Standard Architecture
bridge (LPC to ISA bridge) to address the PC104 bus. Most legacy PC104
modules are I/O mapped and function as expected. The LPC controller is
the subtractive agent of the Intel Legacy Block. All transactions that are
not claimed elsewhere are sent to the LPC controller. The LPC to ISA
bridge does not implement bus mastering cycles or direct memory access
(DMA).
The following tables contain the I/O ports used on the EBC-C413.
JPDIO2
JPDIO2 - Power Enable (+5 VDC) to Pin 49 of DIO2
JPSATA
JPSATA - Serial ATA Device Select
JPATX
JPATX - AT/ATX Power Supply Select
JPMC1
JPMC1 - MC1 Wireless LAN Enable
JPMC2
JPMC2 - MC2 Wireless LAN Enable
JPMSATA
JPMSATA - MC2 mSATA/MiniCard Select
JPLCDP
JPLCDP - LCD Panel Power Configuration
JPBAT
Item
Jumper and Description
Reference
PCU I/O Address
Device
0000h-001Fh
DMA Controller 82C37
0020h-0021h
Interrupt Controller PIC 8259
0024h-0025h
Interrupt Controller
0028h-0029h
Interrupt Controller
002Ch-002Dh
Interrupt Controller
002Eh-002Fh
Forward to Super IO
0030h-0031h
Interrupt Controller
0034h-0035h
Interrupt Controller
0038h-0039h
Interrupt Controller
003Ch-003Dh
Interrupt Controller
0040h-0043h
Timer Counter 8254
004Eh-004Fh
Forward to Super IO
0050h-0053h
Timer Counter 8254
0060h
Keyboard Data Port
0061h
NMI Controller
0062h
8051 download 4K address counter
0064h
Keyboard Status Port
0066h
8051 Download 8-bit Data Port