WIENER, Plein & Baus GmbH
8
www.wiener-d.com
extended mode, the states of the signals are stretched so as to be at least 15 ms long, i.e., long
enough to be visible on the display in a form of a blink.
The following VME bus signals are captured by DTACK* or BERR*:
Data lines:
D0 – D31
Address lines:
A1 – A31
Address modifier lines: AM0 – AM5
Control signals:
AS*, DS0*, DS1*, WRITE*, LWORD*, DTACK*,BERR*
Interrupt Bus:
IACK*, IACKIN*
When in a pseudo-DTACK mode, VM-DBA generates itself a DTACK* upon determining
the absence of DTACK* signal within a timeout period beginning at AS*. This pseudo-
DTACK latches also the above bus signals.
The following signals are captured by BBSY*:
Arbitration bus:
BGIN0* – BGIN7*
The following signals are made visible by stretching:
Interrupt bus:
IRQ1* - IRQ7*
Arbitration bus:
BR0* - BR3*, BCLR*, BBSY*
Utility bus:
SYSRESET*, SYSFAIL*, ACFAIL*
The state of power lines +5V, +3.3V, +12V, and -12V and the SYSCLK line are displayed
“as-is”.
In addition to displaying the state of the VME bus lines, VM-DBA displays on selected
LED’s its operating mode or state, as well as the occurrence of events of importance, as
indicted in the table below.
Row/Col
Color
Label
Function
1L
G
F1
“FPGA Fail” or “Booting”, or “Accessed”, or “IN”, or “IRQ”
1R
R
F2
Sampling rate – “on” indicates 200 MS, “off” is for 100 MS
2L
Y
F3
Active memory –“on” for SPI-1, “off” for the (protected) SPI-0
2R
B
F4
Status of the waveform acquisition – blinking when waveforms
stored, steady “on” when waveforms successfully read out.
3L
R
VD
pseudo DTACK generated (latched)
3R
G I-EN
Interrupt generation and handling active
12R
R
AQ
Continuous waveform writing into circular FIFOs
21
Y VD-E
Pseudo-DTACK generation enabled
29
R CONT
Display “raw”, as-is VME bus line states
30
G PASS
Passive mode
68L
G
H
Blinking when Halt-enabled, steady “on” when display halted
