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8) In this example IRQ 3 was triggering the analyzer at time “cycles = 0”. Following the
IRQ request the interrupter is confirmed by the master (interrupt handler) with IACK.
A(0) to A(3) are set by the master with the IRQ value. The interrupt requestor places
the vector / ID on the data lines after receiving the IACKIN and asserts a DTACK.
Following the BCLR are the VME calls which are issued in response on the interrupt.
Please see the detailed description of the VME interrupt handling in the VITA VME
bus specification for further details.
