Wiener AVM16, Руководство пользователя

Страница: 18 / 33

18
13 nPD "not power down", this bit is set internally to 1
15-14 A1/A0 Channel number 0 to 3 for ofs_dac[0], 4 to 7 for
ofs_dac[1] and so on...
5.4.3 Registers that are sent to all ADC FPGAs too.
The readback of these registers occurs from a shadow register in VIRTEX-5.
cr 0x100 - Control/Mode Register
Bit Name Function
0 ENA General enable. If this bit is not set, AVM16 is
in its groud state. All data are deleted.
1 EXTRIG Enables the trigger input from the front
connector (LVDS). The trigger time is determined
in VIRTEX-5 and sent to all ADC FPGAs, in order
to start the analysis. The next trigger is then
only possible when all data have been transmitted
to VIRTEX-5.
2 LEVTRIG With this bit a trigger is fired when the value
of an ADC input (that is not inhibited by cha_inh
) overcomes the value in trig_level register. The
corresponding ADC FPGA sends the trigger time to
VIRTEX-5 which forwards it to all ADC FPGAs in
order to start the read out.
3 VERBOSE When this bit is set, the pairs of values for
minima and maxima are transmitted (if RAW Mode is
not set).
4 ADCPOL The polarity of the ADC data can be changed here.
By default are ADC data inverted, to analyze
negative pulses. When this bit is set, ADC data
are not inverted, to analyze positive pulses.
Also the RAW data are invereted.
5 SGRD Single Gradient. In the computation of the rise
time only two points with
∆
x=1 are considered.
Normally ∆ x can also be 2 or 4, if the
corresponding y values lie between ¼ and ¾ of the
maximal value.
6 TP_ON
With this bit the test signal can be statically
enabled.
7 PW_ON
With this bit, the analog ADC power supply can be
statically enabled. Otherwise, it is only enabled
when bit 0 (ENA) is set.
act 0x104 - Action register
Bit Name Write/single shot
0 MRST
Master Reset
1 SRST
Synchron Reset for all timers, so that all FPGAs
have the same time reference.