Wiener AVM16, Руководство пользователя

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minimum between the peaks, where the integral for next peak starts, or by
reaching the baseline level for the last peak. With the value in this register it is
possible to end the integration earlier when the number of bins reaches the value.
aclk_shift 0x12C - The ADC clock must have a fixed phase to the FPGA clock, in order to
correctly transmit ADC data. For test purposes it is possible to change the phase,
e.g. in order to determine whether the default phase is set correctly. The default
phase is 0.
Bit ADC Write Read
0
4
8
12 3..0
7..4
11..8
15..12 Execute a step Step executed
1,5,9,13 dto. 0 for positive
step and 1 for
negative step Upper or lower limit
reached, overflow
2,6,10,14 dto. Reset number of
steps to 0 0
160 steps in one or the other direction correspond to ±180°.
lb_test[4] 0x130 to 0x13C - Every one of the 4 SPARTAN-3 FPGAs has a data test register,
for testing the local data bus. These registers should be writable with any 16 bit
value and it should be possible to read this value back.
5.4.4 Registers that are individually available for every channel.
base_line[16] 0x200 to 0x23C - In the FPGA the ADC mean value for each channel is
computed continuously. ADC input test pulses are excluded.
noise_level[16] 0x240 to 0x27C - In the FPGA the noise amplitude is computed for each
channel, by subtracting the minimum value from the maximum value.
Since there is no expected big noise level, these registers have a 5 bit
width (max. 31 noise bins). By readout all maxima and minima are reset
to the present value. The FPGA logic is so designed that noise is not
computed for a given time before and after an input pulse.
q_threshold[16] 0x280 to 0x2BC - The computed data from the integral window are only
delivered if the corresponding integral is higher than the value of this
register. If the value is 0 data are always delivered. Read back is not
possible.
5.4.5 Registers for data readout in single or block transfer mode.
data_range 0x400 to 0x7FC - ADC/QDC data stored in VIRTEX-5 FIFO can be read out
through this address, independently from which address in this range is read, so
that also an incremental block transfer is possible. Single transfers as well as block
transfers BLT and MBLT are allowed.