VMIC VMICPCI-7755, Руководство по эксплуатации продукта

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Timers
3
result, it is not possible to capture the values of all four timers at a give instance in
time. However, by setting this bit to “1”, all four timer outputs will be latched only on
reads to the Timer 1 & 2 Current Count Register (TMRCCR12). Therefore, to capture
the current count of all four timers at the same time, perform a read to the TMRCCR12
first (with a 32-bit read), followed by a read to TMRCCR3 and TMRCCR4. The first
read (to the TMRCCR12 register) causes all four timer values to be latched at the same
time. The subsequent reads to the TMRCCR3 and TMRCCR4 registers do not latch
new count values, allowing the count of all timers at the same instance in time to be
obtained.
Timer 1 & 2 Load Count Register (TMRLCR12)
Timers 1 & 2 are 16-bits wide and obtain their load count from the Timer 1 & 2 Load
Count Register (TMRLCR12), located at offset 0x10 from the address in BAR1. The
mapping of bits in this register are as follows:
When either of these fields are written (either by a single 32-bit write or separate
16-bit writes), the respective timer is loaded with the written value on the next rising
edge of the timer clock, regardless of whether the timer is enabled or disabled. The
value stored in this register is also automatically reloaded on terminal count (or
timeout) of the timer.
Timer 3 Load Count Register (TMRLCR3)
Timer 3 is 32-bits wide and obtains its load count from the Timer 3 Load Count
Register (TMRLCR3), located at offset 0x14 from the address in BAR1. The mapping
of bits in this register are as follows:
When this field is written, Timer 3 is loaded with the written value on the next rising
edge of the timer clock, regardless of whether the timer is enabled or disabled. The
value stored in this register is also automatically reloaded on terminal count (or
timeout) of the timer.
Field Bits Read or Write
Timer 2 Load Count TMRLCR12[31..16] R/W
Timer 1 Load Count TMRLCR12[15..0] R/W
Field Bits Read or Write
Timer 3 Load Count TMRLCR3[31..0] R/W