VMIC VMICPCI-7755, Руководство по эксплуатации продукта

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59
Timers
3
When this field is read, the current count value is latched and returned. There are
two modes that determine how the count is latched depending on the setting of the
“Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2
register description for more information on these two modes.
Timer 4 Current Count Register (TMRCCR4)
The current count of Timer 3 may be read via the Timer 4 Current Count Register
(TMRCCR4), located at offset 0x28 from the address in BAR1. The mapping of bits in
this register are as follows:
When this field is read, the current count value is latched and returned. There are
two modes that determine how the count is latched depending on the setting of the
“Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2
register description for more information on these two modes.
Timer 1 IRQ Clear (T1IC)
The Timer 1 IRQ Clear (T1IC) register is used to clear an interrupt caused by Timer 1.
Writing to this register, located at offset 0x30 from the address in BAR1, causes the
interrupt from Timer 1 to be cleared. This can also be done by writing a “0” to the
appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).
This register is write only and the data written is irrelevant.
Timer 2 IRQ Clear (T12C)
The Timer 2 IRQ Clear (T2IC) register is used to clear an interrupt caused by Timer 2.
Writing to this register, located at offset 0x34 from the address in BAR1, causes the
interrupt from Timer 2 to be cleared. This can also be done by writing a “0” to the
appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).
This register is write only and the data written is irrelevant.
Timer 3 IRQ Clear (T3IC)
The Timer 3 IRQ Clear (T3IC) register is used to clear an interrupt caused by Timer 3.
Writing to this register, located at offset 0x38 from the address in BAR1, causes the
interrupt from Timer 3 to be cleared. This can also be done by writing a “0” to the
appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).
This register is write only and the data written is irrelevant.
Field Bits Read or Write
Timer 4 Count TMRCCR4[31..0] R.O.