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VMICPCI-7755 Product Manual
Timer 4 IRQ Clear (T4IC)
The Timer 4 IRQ Clear (T4IC) register is used to clear an interrupt caused by Timer 4.
Writing to this register, located at offset 0x3C from the address in BAR1, causes the
interrupt from Timer 4 to be cleared. This can also be done by writing a “0” to the
appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).
This register is write only and the data written is irrelevant.
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