VersaLogic STD32 VL-1225, Справочное руководство

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VL-1225/6 Analog Input/Output Board
5-1
Operation
This section describes how to operate the VL-1225/6. Two typical input modes of operation, polled mode,
and interrupt mode are discussed, as well as a discussion of output mode. Code examples written in 80188
assembly language are included in the next section.
Polled Mode Analog Input
Polled mode operation is the simplest method of operating the VL-1225/6 for analog input. It is the
responsibility of the CPU to start each new A/D conversion as desired, and to read the digital results upon
completion.
Polled Mode Steps
• Channel selection and Trigger
• Wait until done and keep High Data
• Read Low Data
• Mask unused bits and/or sign extend
Channel selection and Trigger
Output the desired channel number to the Channel Select register (see page 4-2). This automatically
triggers the A/D circuits to begin converting. The conversion will complete in about 40
µ
S. If desired,
the CPU is free to execute unrelated code, and then return to the next step in the sequence.
Wait until done and keep High Data
Read the Input Data High register until bit D7 (BUSY) = 0. This is best accomplished by reading the
contents of this register directly into the CPU’s accumulator or into an 8-bit variable. The Input Data High
register contains the conversion status bit and some of the high-order data bits of the A/D results. Bit
D7 (BUSY) is set to 1 when the conversion is triggered in the previous step. When BUSY = 0, the A/D
conversion has completed, signaling that both Input Data High and Input Data Low registers contain valid
data. Since the CPU has been reading the Input Data High register in order to test the BUSY bit, the
upper-order bits of the A/D results have already been fetched from the VL-1225/6. It is not necessary to
re-read the Input Data High register.
Read the Low Data
Read the Input Data Low register directly into another CPU register. See page 4-3.
Mask unused bits (Optional)
Bit D7 (BUSY) of the Input Data High register is guaranteed to equal 0, however bits D6 – D3 (or D6 –
D2 in 10-bit resolution mode) are not guaranteed to be stable. The data should be masked to “0” by ANDing
with 07H (or 03H in 10-bit resolution mode). This step can be skipped if the sign extension procedure
described below is performed.
Sign Extension (Optional)
In two’s complement mode, if you’re handling the A/D data using 16-bit variables or CPU registers, it
might be desirable to “sign extend” the 10- or 11-bit value into 16 bits prior to storage or mathematical
manipulation. This is accomplished by duplicating the sign bit (bit D2 (AD10) in 11-bit resolution mode,
or bit D1 (AD9) in 10-bit resolution mode) into all unused bit positions to it’s left. The process of sign
extension inherently masks unused bits with “1” or “0” as appropriate. The software examples show how
this is done with shift instructions.
Operation