VersaLogic STD32 VL-1225, Справочное руководство

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5-2
VL-1225/6 Analog Input/Output Board
Interrupt Mode Analog Input
Interrupt mode eliminates the need to repeatedly poll the Status register while waiting for the A/D
conversion to complete. This frees up the CPU to execute unrelated code while the VL-1225/6 is busy with
an A/D conversion.
Interrupt Mode Steps
• Interrupt Service Routine (ISR)
• Initialize VL-1225/6 for interrupt mode
• Initialize interrupt controller
• Initialize CPU to receive interrupt
• Channel selection and Trigger
Interrupt Service Routine (ISR)
The interrupt service routine reads A/D conversion results from the VL-1225/6 and stores the data
somewhere. Data is input from the Input Data High register first, followed by the Input Data Low register.
Since execution of the ISR is triggered by bit D7 (BUSY) of IDHIGH, data is guaranteed valid upon ISR
entry. It is not necessary to double check the BUSY bit before reading the data. The act of reading the
Input Data Low clears the interrupt request signal.
The ISR can be written to mask unused high-order bits and perform sign-extension for two’s complement
format. If continuous operation is desired, the ISR can select a different channel. Be prepared, however,
for another interrupt within 40
µ
S. If the ISR does not return to the mainline program before this time
delay, ISR recursion will occur. Unless special precautions are taken, the CPU return stack will overflow.
In systems with multiple, non-vectored interrupting devices, the interrupt request status bit D0 (IR) of
ISTAT can be read to verify that the VL-1225/6 is responsible for the interrupt. See page 4-13 for further
information.
Initialize VL-1225/6 for interrupt mode
Set bit D0 (IE) in the Interrupt Control register. See page 4-13 for further information.
Initialize interrupt controller
This involves setting up interrupt vector registers, priority, and unmasking. See your interrupt controller
instruction manual for further information.
Initialize CPU to receive interrupts
This involves preparing the interrupt vector table, and enabling interrupts. See your CPU instruction
manual for further information.
Channel selection and Trigger
Output the desired channel number to the Channel Select register (see page 4-2). This automatically
triggers the A/D circuits to begin converting. An interrupt is generated when the VL-1225/6 completes
a A/D conversion.
Analog Output
Writing to a VL-1225 output channel is as simple as writing one byte of data to the desired output channel
address. Upon writing the data, the appropriate D/A converter will change its output value.
Operation – Interrupt Mode Analog Input