Accept the transmit pulse burst sample to measure its frequency, phase, and
power
RVP901 receives the analog receive waveforms and digitizes IF samples.
The receiver electronics (LNA, RF mixer, IF preamp, and IFDR) can be up to 25 m away from
the RVP902 server chassis. This makes it possible to optimize the locations of the IFDR and
the RVP902. For example, the IFDR could be mounted on the antenna, and the processor
box is in a nearby equipment room.
Amplitude measurement and correction of transmitted pulse (from burst
sample)
The IFDR computing power, in the form of an FPGA that can execute 38.4 billion multiply/
accumulate cycles per second, allows the use of multiple finite impulse response (FIR) filter
arrays to run simultaneously.
The FPGA serve as the first stage of processing of the raw IF data samples. It performs the
down-conversion, band pass, and deconvolution steps that are required to produce (
I
,
Q
)
time series. The time series data are then transferred over a Gigabit Ethernet connection to
the RVP902 server for final processing.
The FIR filter array can buffer up to 80 microseconds of 100 MHz IF samples, and then
compute a pair of 2880-point dot products on those data every 0.83 microseconds. This can
produce over-sampled (
I
,
Q
) time series with a range resolution of 125 m and a bandwidth as
narrow as 30 KHz. The same computation can also yield independent 125 m time series data
from an 80 microseconds compressed pulse, whose transmit bandwidth was approximately
1 MHz.
Finer range resolutions are also possible, down to a minimum of 25 m. In RVP900, the bin
spacing of the (
I
,
Q
) data can be set to any value between 25 ... 2000 m. Range bins are
placed accurately to 2.2 m of any selected grid, which does not have to be an
integer multiple of the sampling clock. However, when an integer multiple (
N
x 8.333 m) is
selected, the error in bin placement effectively drops to 0.
Dual-polarization radars that are capable of simultaneous reception for both horizontal and
vertical channels are interfaced to the same piece of hardware. Because the sampling time is
highly coherent, ZDR biases do not occur in high reflectivity gradients. The 16-bit
I
and
Q
resolution is passed to the RVP902 server for both H and V.
The following figure shows a calibration plot for a 16-bit IFDR with the digital filter matched
to a 2 microseconds pulse. The performance in this case is >105 dB dynamic range.
RVP900 User Guide
M211322EN-J
24
Содержание RVP900
Страница 1: ...M211322EN J User Guide RVP900 Digital Receiver and Signal Processor RVP900...
Страница 19: ...RVP9IFD China RoHS Compliance RVP901 AC and RCP903 China RoHS Compliance Chapter 2 Product Overview 17...
Страница 22: ...RVP900 User Guide M211322EN J 20...
Страница 88: ...RVP900 User Guide M211322EN J 86...
Страница 170: ...RVP900 User Guide M211322EN J 168...
Страница 236: ...RVP900 User Guide M211322EN J 234...
Страница 390: ...RVP900 User Guide M211322EN J 388...
Страница 434: ...Figure 68 ASR9 WSP with RVP7 Architecture RVP900 User Guide M211322EN J 432...
Страница 456: ...Figure 82 J90 to J111 Wiring Diagrams RVP900 User Guide M211322EN J 454...
Страница 457: ...Figure 83 J13 Wiring Diagram Appendix H TDWR Customizations 455...
Страница 468: ...RVP900 User Guide M211322EN J 466...
Страница 482: ...RVP900 User Guide M211322EN J 480...
Страница 483: ......
Страница 484: ...www vaisala com...