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Appendix
A. BIOS Post Code
AMIBIOS8 Check Point and Beep Code List
The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The
following table describes the type of checkpoints that may occur during the POST portion of the BIOS.
Checkpoint Description
Before D0
If boot block debugger is enabled, CPU cache-as-RAM functionality is enabled at this point.
Stack will be enabled from this point.
D1
Early super I/O initialization is done including RTC and keyboard controller.
Serial port is enabled at this point if needed for debugging. NMI is disabled.
Perform keyboard controller BAT test. Save power-on CPUID value in scratch CMOS. Go to flat
mode with 4GB limit and GA20 enabled.
D2 Verify the boot block checksum. System will hang here if checksum is bad.
D3
Disable CACHE before memory detection. Execute full memory sizing module.
If memory sizing module not executed, start memory refresh and do memory sizing
in Boot block code. Do additional chipset initialization.
Re-enable CACHE. Verify that flat mode is enabled.
D4 Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5
Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS
now executes out of RAM. Copies compressed boot block code to memory in right segments.
Copies BIOS from ROM to RAM for faster access. Performs main BIOS checksum and updates
recovery status accordingly.
D6
Both key sequence and OEM specific method is checked to determine if BIOS
recovery is forced. If BIOS recovery is necessary, control flows to checkpoint E0. See
Bootblock Recovery Code Checkpoints section of document for more information.
D7
Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to
system memory and control is given to it. Determine whether to execute serial flash.
D8 The Runtime module is uncompressed into memory. CPUID information is stored in memory.
D9
Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into
memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow
areas but closing SMRAM.
DA
Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See
POST Code Checkpoints section of document for more information.
DC System is waking from ACPI S3 state.
03
Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data
area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as
mentioned in the Kernel Variable "wCMOSFlags."