TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R28
Design-in
Page 110 of 164
2.6.4
Secure Digital Input Output interface (SDIO)
☞
The SDIO Secure Digital Input Output interface is not available on MPCI-L2 series modules.
2.6.4.1
Guidelines for SDIO circuit design
☞
The functionality of the SDIO interface pins is not supported by TOBY-L2 modules “00”, “01” and
“60” product versions: the pins should not be driven by any external device.
TOBY-L2 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1,
SDIO_D2, SDIO_D3, SDIO_CLK, SDIO_CMD) designed to communicate with an external u-blox short
range Wi-Fi module.
Combining a u-blox cellular module with a u-blox short range communication module gives designers
full access to the Wi-Fi module directly via the cellular module, so that a second interface connected
to the Wi-Fi module is not necessary. AT commands via the AT interfaces of the cellular module
(UART, USB) allows full control of the Wi-Fi module from any host processor, because Wi-Fi control
messages are relayed to the Wi-Fi module via the dedicated SDIO interface (for more details, see the
Wi-Fi AT commands in the u-blox AT Commands Manual
and see the Wi-Fi / Cellular Integration
Application Note
and
show an application circuit for connecting TOBY-L2 cellular modules (except
“00”, “01” and “60” product versions) to u-blox ELLA-W131 short range Wi-Fi 802.11 b/g/n modules:
The SDIO pins of the cellular module are connected to the related SDIO pins of the u-blox ELLA-W1
series short range Wi-Fi module, with appropriate low value series damping resistors to avoid
reflections and other losses in signal integrity, which may create ringing and loss of a square wave
shape.
The most appropriate value for the series damping resistors on the SDIO lines depends on the
specific line lengths and layout implemented. In general, the SDIO series resistors are not strictly
required, but it is recommended to slow the SDIO signal, for example with 22
or 33
resistors,
and avoid any possible ringing problem without violating the rise / fall time requirements.
The V_INT supply output pin of the cellular module is connected to the shutdown input pin
(SHDNn) of the two LDO regulators providing the 3.3 V and 1.8 V supply rails for the u-blox
ELLA-W1 series Wi-Fi module, with appropriate pull-down resistors to avoid an improper switch on
of the Wi-Fi module before the switch-on of the V_INT supply source of the cellular module SDIO
interface pins.
The GPIO1 pin of the cellular module is connected to the active low full power down input pin (PDn)
of the u-blox ELLA-W1 series Wi-Fi module, implementing the Wi-Fi enable function.
The configuration pin (CFG) of the u-blox ELLA-W1 series Wi-Fi module is connected to ground by
means of a proper pull-down resistor for operation without sleep clock
The sleep clock input pin (SLEEP_CLK) of the u-blox ELLA-W1 series Wi-Fi module is left not
connected, because an external clock source is not required.
The WLAN LED open drain output pin (LED_0) of the u-blox ELLA-W1 series Wi-Fi module is
connected to an LED with appropriate current limiting resistor, indicating Wi-Fi activity as
additional optional feature.
The WLAN antenna RF input/output (ANT1) of the u-blox ELLA-W131 Wi-Fi module is connected
to a Wi-Fi antenna with an appropriate series Wi-Fi 2.4 GHz band-pass filter specifically designed
for the coexistence between the Wi-Fi 2.4 GHz RF signals (2402...2482 MHz) and the LTE band 7
RF signals (2500...2690 MHz), as for example the Wi-Fi BAW 2.4 GHz band-pass filter TDK EPCOS
B9604, or the TriQuint 885071, or the TriQuint 885032 or the Avago ACPF-7424, or the Taiyo
Yuden F6HF2G441AF46.
All GND pins of the cellular module and the u-blox ELLA-W131 module are connected to ground.
All the other pins of the u-blox ELLA-W1 series Wi-Fi module are intended to be not connected.
