TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R28
Design-in
Page 108 of 164
Additional considerations
If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to
the corresponding 1.8 V input of the module (DCE) can be implemented as an alternative low-cost
solution, by means of an appropriate voltage divider. Consider the value of the pull-up integrated at
the input of the module (DCE) for the correct selection of the voltage divider resistance values and
mind that any DTE signal connected to the module must be tri-stated or set low when the module is
in power-down mode and during the module power-on sequence (at least until the activation of the
V_INT supply output of the module), to avoid latch-up of circuits and allow a proper boot of the module
(see the remark below).
Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the corresponding
3.0 V input of the Application Processor (DTE) can be implemented by means of an appropriate
low-cost non-inverting buffer with open drain output. The non-inverting buffer should be supplied by
the V_INT supply output of the cellular module. Consider the value of the pull-up integrated at each
input of the DTE (if any) and the baud rate required by the application for the appropriate selection of
the resistance value for the external pull-up biased by the application processor supply rail.
☞
If power saving is enabled the application circuit with the TXD and RXD lines only is not
recommended. During command mode the DTE must send to the module a wake-up character or
a dummy “AT” before each command line (see section
for the complete description), but
during data mode the wake-up character or the dummy “AT” would affect the data
communication.
☞
Do not apply voltage to any UART interface pin before the switch-on of the UART supply source
(V_INT), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals
connected to the cellular module cannot be tri-stated or set low, insert a multi channel digital
switch (e.g. TI SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections
and set to high impedance before V_INT switch-on.
☞
ESD sensitivity rating of UART interface pins is 1 kV (Human Body Model according to
JESD22-A114). Higher protection level could be required if the lines are externally accessible and it
can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array)
close to accessible points.
☞
If the UART interface pins are not used, they can be left unconnected on the application board, but
it is recommended providing accessible test points directly connected to all the UART pins (TXD,
RXD, RTS, CTS, DTR, DSR, DCD, RI) for diagnostic purpose, in particular providing a 0
series
jumper on each line to detach each UART pin of the module from the DTE application processor.
2.6.2.2
Guidelines for UART layout design
The UART serial interface requires the same consideration regarding electro-magnetic interference
as any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog
inputs, since the signals can cause the radiation of some harmonics of the digital data frequency.
