TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R28
Design-in
Page 104 of 164
2.6.1.2
Guidelines for USB layout design
The USB_D+ / USB_D- lines require accurate layout design to achieve reliable signaling at the high
speed data rate (up to 480 Mb/s) supported by the USB serial interface.
The characteristic impedance of the USB_D+ / USB_D- lines is specified by the Universal Serial Bus
Revision 2.0 specification
. The most important parameter is the differential characteristic
impedance applicable for the odd-mode electromagnetic field, which should be as close as possible to
90
differential. Signal integrity may be degraded if PCB layout is not optimal, especially when the
USB signaling lines are very long.
Use the following general routing guidelines to minimize signal quality problems:
Route USB_D+ / USB_D- lines as a differential pair
Route USB_D+ / USB_D- lines as short as possible
Ensure the differential characteristic impedance (Z
0
) is as close as possible to 90
Ensure the common mode characteristic impedance (Z
CM
) is as close as possible to 30
Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled
differential micro-strip or buried stripline: avoid any stubs, abrupt change of layout, and route on
clear PCB area
provide two examples of coplanar waveguide designs with differential
characteristic impedance close to 90
and common mode characteristic impedance close to 30
.
The first transmission line can be implemented in case of 4-layer PCB stack-up herein described, the
second transmission line can be implemented in case of 2-layer PCB stack-up herein described.
35
µ
m
35
µ
m
35
µ
m
35
µ
m
270
µ
m
270
µ
m
760
µ
m
L1 Copper
L3 Copper
L2 Copper
L4 Copper
FR-4 dielectric
FR-4 dielectric
FR-4 dielectric
350
µ
m 400
µ
m
400
µ
m
350
µ
m
400
µ
m
Figure 55: Example of USB line design, with Z
0
close to 90
and Z
CM
close to 30
, for the described 4-layer board layup
35
µ
m
35
µ
m
1510
µ
m
L2 Copper
L1 Copper
FR-4 dielectric
740
µ
m 410
µ
m
410
µ
m
740
µ
m
410
µ
m
Figure 56: Example of USB line design, with Z0 close to 90
and ZCM close to 30
, for the described 2-layer board layup