ZED-F9T - Integration Manual
3.3.11.5.1.1 Read access forms
There are two forms of DDC read transfer. The "random access" form includes a slave register
address and thus allows any register to be read. The second "current address" form omits the
register address. If this second form is used, then an address pointer in the receiver is used to
determine which register to read. This address pointer will increment after each read unless it
is already pointing at register 0xFF, the highest addressable register, in which case it remains
unaltered. The initial value of this address pointer at start-up is 0xFF, so by default all current
address reads will repeatedly read register 0xFF and receive the next byte of message data (or 0xFF
if no message data is waiting).
Figure 14
shows the format of the random access form of the request.
Following the start condition from the master, the 7-bit device address and the
RW
bit (which is a
logic low for write access) are clocked onto the bus by the master transmitter. The receiver answers
with an acknowledge (logic low) to indicate that it recognizes the address. Next, the 8-bit address
of the register to be read must be written to the bus. Following the receiver's acknowledgement,
the master again triggers a start condition and writes the device address, but this time the
RW
bit
is a logic high to initiate the read access. Now, the master can read 1 to
N
bytes from the receiver,
generating a not-acknowledge and a stop condition after the last byte being read.
Figure 14: DDC random read access
The format of the current address read request is:
Figure 15: DDC current address read access
UBX-19005590 - R01
3 Receiver functionality
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