ZED-F9T - Integration Manual
to-back read and write access). When no data is available to be written to the receiver,
MOSI
should
be held logic high, i.e. all bytes written to the receiver are set to 0xFF.
To prevent the receiver from being busy parsing incoming data, the parsing process is stopped after
50 subsequent bytes containing 0xFF. The parsing process is re-enabled with the first byte not equal
to 0xFF.
If the receiver has no more data to send, it sets
MISO
to logic high, i.e. all bytes transmitted decode
to 0xFF. An efficient parser in the host will ignore all 0xFF bytes which are not part of a message and
will resume data processing as soon as the first byte not equal to 0xFF is received.
3.3.11.2.3 Back-to-back read and write access
The receiver does not provide any write access except for writing UBX and NMEA messages to
the receiver, such as configuration or aiding data. For every byte written to the receiver, a byte will
simultaneously be read from the receiver. While the master writes to
MOSI
, at the same time it needs
to read from
MISO
, as any pending data will be output by the receiver with this access. The data
on
MISO
represents the results from a current address read, returning 0xFF when no more data is
available.
Figure 12: SPI back-to-back read/write access
3.3.11.3 USB port
A single USB port is provided for host communication purposes. See the ZED-F9T Data sheet [
1
]
for availability. This port can be used for communication purposes and to power the positioning chip
or module.
The ZED-F9T module supports only self-powered mode operation in which the receiver is supplied
from its own power supply. The V_USB pin is used to detect the availability of the USB port, i.e.
whether the receiver is connected to a USB host.
USB bus powered mode is not supported.
The voltage range for V_USB is specified from 3.0 V to 3.6 V, which differs slightly from the
specification for VCC.
The boot screen is retransmitted on the USB port after the enumeration. However,
messages generated between boot-up of the receiver and USB enumeration are not visible
on the USB port.
3.3.11.4 Extended TX timeout
If the host does not communicate over SPI or DDC for more than approximately 2 seconds, the
device assumes that the host is no longer using this interface and no more packets are scheduled
for this port. This mechanism can be changed by enabling "extended TX timeouts", in which case
the receiver delays idling the port until the allocated and undelivered bytes for this port reach 4 kB.
UBX-19005590 - R01
3 Receiver functionality
Page 30 of 80
Advance Information
