NORA-W10 series - System integration manual
UBX-22005601 - R04
Module integration
Page 12 of 56
C1-Public
2
Module integration
2.1
CPU
NORA-W10 series modules includes a Harvard Architecture Xtensa LX7 dual core CPU operating at
an internal clock frequency of up to 240 MHz. The Open CPU architecture allows custom advanced
applications running on the CPU.
The NORA-W10 architecture includes the following memories:
•
384 KByte ROM for booting and core functions
•
512 KByte SRAM for data and instruction
•
8 Mbyte FLASH for code storage, including hardware encryption to protect programs.
•
4 kbit EFUSE (non-erasable memory) for MAC addresses, module configuration, flash encryption,
and chip ID
2.2
Power modes
NORA-W10 series modules are power efficient devices capable of operating in different power saving
modes and configurations. Different sections of the module can be powered off when they are not
needed, and complex wake up events can be generated from different external and internal inputs.
For more information about power modes, see the Espressif ESP32-S3 Datasheet
2.2.1
Low Power mode with Low Frequency Clock
NORA-W10 series modules do not have an internal low power oscillator (LPO) or low frequency crystal
(LFXTAL), which is required for low power modes. If low power mode is required, an external high
precision, +/- 20 ppm, 32.768 kHz crystal must be connected between pins
XTAL_32K_N (Pin B6)
and
XTAL_32K_P
(Pin C6)
.
On EVK-NORA-W10, the crystal is connected to
XTAL_32K_N (Pin B6)
and
XTAL_32K_P
(Pin C6)
using a jumper configuration in order to use these as GPIOs when Low Power Mode is not in use, as
shown in
Figure 3: Low Frequency Clock
2.3
Power supply
The power for NORA-W10 series modules is supplied through
VCC
and
VCC_IO
pins by DC voltage.
⚠
The power supply circuit must be able to source the peak current of the power modes consuming
highest power. Note that the current drawn from
VCC
and
VCC_IO
can vary significantly based
on Wi-Fi power consumption profiles.