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Ultra DMA/33 Peripheral Component Interconnect adapter card. Ultra DMA uses
the same 40-pin Integrated Drive Electronics interface cable as PIO and DMA.
Options:
Disabled /
Mode 0 / Mode 1 / Mode 2
3.3.2 Memory Cache
This setting allows you to tweak the various cache settings for optimal performance
of your system.
Press Enter to display the various cache settings.
PhoenixBIOS Setup Utility
Main
Advanced Security Power Boot Exit
Memory Cache
Item Specific Help
Cache System BIOS area:
Cache Video BIOS area:
Cache Base 0-512K:
Cache Base 512K-640K:
Cache Extended Memory Area:
Cache A000 – AFFF:
Cache B000 – BFFF:
Cache C800 – CBFF:
Cache CC00 – CFFF:
Cache D000 – D3FF:
Cache D400 – D7FF:
Cache D800 – DBFF:
Cache DC00 – DFFF:
Cache E000 – E3FF:
Cache E400 – E7FF:
Cache E800 – EBFF:
Cache EC00 – EFFF:
[Write Protect]
[Write Protect]
[Write Back]
[Write Back]
[Write Back]
[Disabled]
[Disabled]
[Disabled]
[Disabled]
[Disabled]
[Disabled]
[Disabled]
[Disabled]
[Write Protect]
[Write Protect]
[Write Protect]
[Write Protect]
Controls caching of
system BIOS area.
F1
Help
↑↓
Select Item
-/+
Change Values
F9
Setup Defaults
Esc
Exit
←
→
Select Menu
Enter
Select
X
Sub-Menu
F10
Previous Values
Cache System BIOS Area
This feature is only available when the system BIOS is shadowed. It enables or
disables the caching of the system BIOS ROM at F0000h-FFFFFh via the L2 cache.
This greatly speeds up accesses to the system BIOS. However, this does not
necessarily make the system perform better because the OS does not need to
access the system BIOS often.
As such, it would be a waste of L2 cache bandwidth to cache the system BIOS
instead of data that are more critical to the system's performance. In addition, if any
program writes into this memory area, it will result in a system crash. So, it is
recommended that you write protect this area for optimal system performance.
Options: NULL /
Write Protect
Cache Video BIOS Area
This feature is only valid when the video BIOS is shadowed. It enables or disables
the caching of the video BIOS ROM at C0000h-C7FFFh via the L2 cache. This
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