Tomcat i875PF S5105
Chapter 3: BIOS Setup
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3.4 – Advanced Chipsets Features
In Advanced Chipset Features, you will be abled to adjust many of the chipset special features.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
CAS Latency Time
Active to Precharge Delay
DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
System BIOS Cacheable
Video BIOS Cacheable
Delay Prior to Thermal
DRAM Data Integrity Mode
[By SPD]
[2]
[8]
[4]
[4]
[Enabled]
[Disabled]
[16 Min]
[ECC]
Item Help
_________________________
Menu Level
►
↑↓←→
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
DRAM Timing Selectable:
Select SPD setting SDRAM timing by SPD.
Manual / By SPD
CAS Latency Time:
This setting defines the number of cycles after a read command until output starts.
2 / 2.5 / 3
Active to Precharge Delay:
This item controls the number of DRAM clocks used for DRAM parameters.
8 / 7 / 6 / 5
DRAM RAS# to CAS# Delay:
This field lets you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
4 / 3 / 2
DRAM RAS# Precharge:
This item controls the idle clocks after issuing a precharge command to the DRAM.
4 / 3 / 2
System BIOS Cacheable:
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result.
Disabled / Enabled
