Installation / Preparation for Commissioning
TR-Electronic GmbH 2020, All Rights Reserved
Printed in the Federal Republic of Germany
Page 26 of 91
TR-ECE-BA-GB-0163 v03
10/07/2020
3.4.2 SSI interface (optional)
In addition to the EtherNet/IP™ interface, the measuring system can be equipped with a synchronous-
serial absolute-value interface instead of an incremental interface.
This additional interface is not evaluated in relation to safety and may not
be used for safety-related purposes!
The interface is typically used for control purposes when transferring
absolute value data to a second non-safety-related controller.
3.4.2.1 Signal characteristics
In power-down mode, Data+ and Clock+ are set to high. In the diagram below, this corresponds to the
Time before point
(1)
.
When the clock signal changes from High to Low
(1)
for the first time, the device-internal re-triggerable
monoflop is set to monoflop time t
M
.
The time t
M
determines the lowest transmission frequency (T = t
M
/ 2). The upper cutoff frequency
results from the sum of all signal propagation times and is additionally limited by the built-in filter
circuits.
With each further falling clock edge, the active state of the monoflop is extended by the time t
M
– this
happens last at point
(4)
.
Setting the monoflop
(1)
causes the bit-parallel data pending at the internal parallel-to-serial converter
to be stored by an internally generated signal in an input latch of the shift register. This ensures that
the data does not change during the transmission of an actual position value.
When the clock signal changes from Low to High
(2)
for the first time, the most significant device
information bit (MSB) is applied to the serial data output. With each further rising edge, the next lower-
order bit is pushed to the data output.
When the clock rate has ended, the data lines are kept at 0 V (low) for the duration of the
monoflop time t
M
(4)
. This also results in the minimum pause time t
p
, which must be maintained
between two consecutive clock sequences and is 2 * t
M
.
The evaluation electronics read the data already at the first rising clock edge. Various factors result in
a delay time t
V
>100 ns, without cables. The measuring system data push to the output is thus delayed
by the time t
V
. Therefore, a “Pause-1” is read at time
(2)
. This must be discarded or used for line break
monitoring in conjunction with a “0” after the LSB data bit. The MSB data bit is read only at time
(3)
.
Therefore, the clock number must always be one higher (n+1) than the number of data bits to be
transmitted.
