TQ Ma8XxS, Руководство пользователя

Страница: 33 / 50

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 28
The selected chip SE050 from NXP provides additional smartcard interfaces according to ISO14443 and ISO7816 besides the I2C
interface. The connection of the antenna for ISO 14443 or the sensor for ISO 7816 must be made on the base board.
Since the SMARC standard does not provide any pins for the smartcard interfaces, the signals for the interfaces according to
ISO14443 and ISO7816 are connected to unused SMARC pins.
If the SE050 is equipped as an option, but no ISO14443 and ISO7816 devices are to be operated, the signals on the main board
are to be wired as follows:
Figure 26: Connecting the NC-Pins
(Source:
NXP )
3.6 Unused CPU signals
CPU signals, which are not yet used by other functions and interfaces, are made available for optional use at unused SMARC pins.
Among other things, the complete parallel CSI interface is led out. The signals do not conform to the SMARC specification and
are therefore connected by optional 0-Ω bridges. The 0-Ω bridges are not equipped as standard.
Note: Alternative functions of CPU signals
These signals and their use do not comply with the SMARC specification and are therefore not
connected to the SMARC connector of any standard TQMa8XxS. For customized TQMa8XxS and
indicating that they are not covered by the SMARC standard, these signals can be made available to
SMARC connector through 0 Ω bridges.
Table 18: Optional CPU signals
SMARC pin Signal i.MX 8X Alternative function
/ I2C_CAM0_CK CSI_D00 TAMPER_OUT0
CSI0_TX– / I2C_CAM0_DAT CSI_D01 TAMPER_OUT1
CSI_D02 TAMPER_OUT2
CSI0_CK– CSI_D03 TAMPER_OUT3
C CSI_D04 TAMPER_OUT4
CSI0_RX0– CSI_D05 TAMPER_IN0
C CSI_D06 TAMPER_IN1
CSI0_RX1– CSI_D07 TAMPER_IN2
PC CSI_HSYNC TAMPER_IN4
PCIE_D_TX– CSI_VSYNC TAMPER_IN3
PC CSI_MCLK GPIO3_IO01
PCIE_D_RX– CSI_PCLK GPIO3_IO00
HDA_SYNC / I2S2_LRCK CSI_EN GPIO3_IO02