User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH
Page 13
3.2.2
Memory
3.2.2.1
LPDDR4 SDRAM
LPDDR4 SDRAM with an effective memory bandwidth of 32 bits is used on the TQMa8XxS. The fifth byte lane of the i.MX 8X CPU
is unused.
i.MX 8X
DQ[15:0]_A
LPDDR4
DQ[15:0]_B
x16
x16
CA[5:0]_A
Channel0
Channel1
CA[5:0]_B
Figure 4:
Block diagram LPDDR4
The interface timing corresponds to the JEDEC standard LPDDR4-2400 with a max. clock rate of 1200 MHz.
The use of LPDDR4 memory eliminates the ECC feature of the RAM controller. However, special ECC memories can be used that
protect the memory content via ECC independently of the controller. Through correspondingly fewer refresh cycles of the cells,
the power consumption is thereby reduced or the memory is used energy neutral (compared to use without ECC) at higher
temperatures.
The IO voltage of the LPDDR4 is 1.1 V.
The standard memory size of the TQMa8XxS is 2 GByte. Variants with 1 GByte and 4 GByte are available.
Attention: Malfunction
The TQMa8XxS uses a specially developed RAM timing. Each memory expansion level required its own
LPDDR4 configuration.
The standard memory for TQMa8XxS is Samsungs K4F6E3S4HM-GFCL03V (LPDDR4-1866 2048Mx32).
3.2.2.2
eMMC NAND flash
An eMMC is available on the TQMa8XxS as non-volatile memory for programs and data (e.g. bootloader, operating system,
application). The following figure shows the interface of the eMMC to the i.MX 8X:
i.MX 8X
eMMC 5.x
EMMC0_CLK
EMMC0_CMD
CLK
CMD
EMMC0_DATA[7:0]
DAT[7:0]
EMMC0_RESET_B
RST#
EMMC0_STROBE
DS
VCC
VCCQ
1,8 V 3,3 V
Figure 5:
Block diagram eMMC
