TMP91C824
91C824-80
2008-02-20
3.6
Chip Select/Wait Controller
On the TM91C824, four user-specifiable address areas (CS0 to CS3) can be set. The data bus
width and the number of waits can be set independently for each address area (CS0 to CS3
and others).
The pins
CS0
to
CS3
(which can also function as port pins P60 to P63) are the respective
output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas,
the corresponding
CS0
to
CS3
pin outputs the chip select signal for the specified address area
(in ROM or SRAM). However, in order for the chip select signal to be output, the port 6
function register P6FC must be set.
CS2A
To
CS2E
(CS pin except
CS0
to
CS3
) are made by MMU.
These pins are
CS
pin that area and BANK value is fixed without concern in setting of
CS/WAIT controller.
The areas CS0 to CS3 are defined by the values in the memory start address registers
MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3.
The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify
the master enable/disable status the data bus width and the number of waits for each address
area.
The input pin controlling these states is the bus wait request pin (
WAIT
).
3.6.1 Specifying
an
Address
Area
The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to
MSAR3) and memory address mask registers (MAMR0 to MAMR3).
At each bus cycle, a compare operation is performed to determine if the address on the
specified a location in the CS0 to CS3 area. If the result of the comparison is a match, this
indicates an access to the corresponding CS area. In this case, the
CS0
to
CS3
pin
outputs the chip select signal and the bus cycle operates in accordance with the settings in
chip select/wait control register B0CS to B3CS. (See 3.6.2 “Chip Select/Wait Control
Registers”.)
