Circuit Operating Descriptions
7-25
Speed error detection
HSW
generation
Phase error detection
Digital filter
Digital filter
PWM
conversion
Digital filter
Bias value addition
RECCTL generation
Phase detection
Digital filter
Speed error detection
PBCTL amplifier
RECCTL head
Kp
Kp
Kv
Kv
(Drum speed gain)
(Drum phase gain)
(Capstan phase gain)
CFG amplifier
VSYNC separation
circuit
composite sync
signal
Vertical sync signal
DPG comparator
DFG amplifier
PWM
conversion
Motor driver
Motor driver
Carrier rejection filter
Carrier rejection filter
M
Drum motor
M
Capstan motor
CFG signal
DPG signal
DFG signal
Remark The broken line indicates the internal processing of the MICOM
Fig. 7-17 Block Diagram
Содержание D-VR3SU
Страница 3: ...CONTENTS ...
Страница 4: ...MEMO ...
Страница 10: ...Precautions 1 6 MEMO ...
Страница 22: ...Reference Information 2 12 MEMO ...
Страница 24: ...Product Specification 3 2 MEMO ...
Страница 25: ...4 1 4 Operating Instructions ...
Страница 88: ...5 22 Disassembly and Reassembly MEMO ...
Страница 100: ...6 12 Alignment and Adjustments MEMO ...
Страница 115: ...Circuit Operating Descriptions 7 15 Fig 7 12 IC601 Block Diagram ...
Страница 148: ...Circuit Operating Descriptions 7 48 MEMO ...
Страница 160: ...VCR Deck Operating Description 8 12 Fig 8 14 Mecha Timing Chart ...
Страница 174: ...VCR Deck Operating Description 8 26 MEMO ...
Страница 200: ...Exploded View and Parts List 10 8 MEMO ...
Страница 216: ...11 16 Electrical Parts List MEMO ...
Страница 217: ...1 1 SHIBAURA 1 CHOME MINATO KU TOKYO 105 8001 JAPAN ...