Toshiba D-VR3SU, Руководство по обслуживанию

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Circuit Operating Descriptions
7-5
7-2-1 DIC1 Processor Internal Architecture Diagram
Fig. 7-6
SPARC Processor Core
Data
I - Cache Memory/
Cache
Audio DSP Host
And And
Memory Graphics SPARC Processor Core
Data
I - Cache Memory/
Cache
Audio DSP Host
And And
Memory Graphics
Video
Interface
Audio
Interface Host
Interface
Bitstream/
Storage
Inter face 1394
Link
Interface
Serial I/O
DENC
Video DSP
and memory
Motion
Estimator
and memory
Memory/
Cpntroller
16/32
SPDIF
4Port
2Port
1X10 YUV
64
32
SDRAM
7-2-2 A/V Processor (DIC1) Functional description
1) SPARC Processors
Two 32-bit SPARC processors, one dedicated to video processing and the other assigned general system tasks
and audio processing, perform three classes of functions: system processing, audio processing, and high-level
control flow and decision-making tasks for video processing. Optionally, they can also perform 2D graphics
and host functions.
The DMN8602 also support multiple video inputs, windowed video ad graphics with arbitrarily relocatable
and resizable windows, PIP (Picture-in-Picture), letterbox, and side-by-side display of SD sources.
2) Host Interface
The host communication functions include initializing the DMN-8602 device, downloading software to the
local SDRAM, sending commands, monitoring status, and downloading graphics data such as OSD bitmap.