P440 Data Sheet / User Guide
DRAFT
35
4.4.4 Ethernet and IP Addressing
Ethernet 10/100 is provided either through the standard Ethernet RJ45 Jack or as Ethernet RMII
signal lines through the Ethernet Mezzanine Connector (J8). As such, the RMII signals cannot be
interfaced to directly. The user must provide a carrier board and an Ethernet PHY chip.
The communications rate through this interface is limited not only by the Ethernet 10/100 protocol
but also by the processing capability of the connected computer and various system overheads. For
example, when transferring radar scans, the typical maximum transfer rate using a low grade laptop
PC is approximately 2 Mbps. This transfer rate can be increased by a factor of four by using a faster
computer and by running C code unencumbered with displays and other user interface features. For
details, see the UWB radar sample C application,
150-0107D MRM Sample C Application
. This
document can be found on the Time Domain website or on your release disk.
The IP address of a unit is assigned in one of two ways. If the P440 came as part of a Development
Kit or a PulsON Lab then the IP addresses will be set at the factory to 192.168.1.x, where “x” is
indicated on a label mounted on the P440’s RJ45 jack. If the P440 was ordered as an “Industrial
Module” then the IP address is set by the Dynamic Host Configuration Protocol (DHCP).
As a side note, the Node ID of the P440 is set in a similar fashion. If the P440 came as part of a Kit
then the Node ID will be set to “x.” If the P440 came as an Industrial Module, then the Node ID is set
at the factory and can be determined through the API or any of the GUIs provided with the system.
Instructions on how to connect to the P440 via Ethernet or change the IP address and Node ID are
provided in the following document:
320-0328 Connecting to P440 with Ethernet
.
4.4.5 CAN
The CAN interface is provided with a TI SN65HVD231 CAN line driver. That driver provides a 5
volt differential signal. For additional details on the driver, a link is provided to the TI part. The
maximum data rate is 1 Mbps.
http://www.ti.com/lit/ds/symlink/sn65hvd231.pdf
Time Domain’s application note
320-0326 CAN Interface Application Note
provides additional
information on the software interface. This document is available on the Time Domain website.
4.5 GPIO
The P440 has fifteen user-definable general purpose input/output (GPIO) pins. Most of these pins
operate on 3.3 Vdc but there are several that operate at 1.8 Vdc. Approximately half come from the
ARM processor and the remaining ones are connected to the FPGA. These pins can be defined as
inputs, outputs, or as having a special function. The SPI pins are special function pins. If the user
chooses not to use the SPI interface, then the SPI pins can be reallocated for general use. The state
and direction of these pins are controlled through the software API.
The GPIO pins are not associated with a specific connector but are instead distributed through the
various connectors. Some GPIO pins are available from multiple connectors.
Figure 23
lists the
various GPIO pins and their associated connector and pin number:
