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P440 Data Sheet / User Guide
The protocol used to communicate with the P440 is fully defined in the various Time Domain API
Specifications, various C and MATLAB examples, and in the document “
Using the USB and Serial
specifications. All of these resources are provided on the delivery disks and are also available on the
Time Domain website,
4.4.1 USB 2.0 High Speed Device
The P440 supports USB 2.0 High Speed Device connection through the USB Data microUSB jack
(J5). When connecting through J5 it is important to remember that this jack only provides the data
communications lines to the P440. To power the board, the user should apply power to the board
either through the USB Power microUSB jack (J13), through the locking connector (J11) or through
pin 21 on the User Mezzanine connector.
The maximum data rate for the USB is 480 Mbps. However, the maximum effective throughput will
be limited by many factors, including the speed of the Host computer, the specific implementation of
the USB driver, processing overhead at the P440, and processor overhead at the Host computer.
4.4.2 User Serial
The User Serial interface is RS-232 Universal Asynchronous Receiver/Transmitter (UART) Serial
operating at 3.3V TTL logic levels. The maximum speed of the interface is 115.2 kbps. Lower rates
of 9.6, 19.2, 38.4, and 57.6 kbps are also supported. The default rate is 115.2 kbps.
However, the maximum rate is largely a function of the ability of the system to drive the cable
capacitance. If a shorter cable is used or if the user provides an external line driver, then the
communications r
a
te can be increased by factors of 2 up to 921.6 kbps. Operation at these higher
ranges is also limited by the serial interface circuit on the user-provided Host computer. The
maximum length of cable must be determined empirically. Time Domain has found that a cable
length of 1 foot (30 cm) will support the 460.8 kbps rate quite reliably.
User Serial is provided on the Locking connector (J11), the User Mezzanine connector (J10), and the
User Header (J7).
The Serial interface uses 3.3 volt logic. Do not connect 5 volt serial cables to the P440. In fact, do not
connect any serial cables that operate at greater than 3.3 volts. The increased voltage will physically
damage the P440.
4.4.3 SPI
The SPI interface is designed to operate at a maximum clock rate of 16.0 MHz with signals operating
at 3.3V TTL levels. The actual throughput of the link is limited by the various communications
overheads. However, transfer rates of 6-7 Mbps have been achieved using an un-optimized system.
The SPI port consists of five signals. Four of these are the typical SPI signals: CLK, CSn, MOSI, and
MISO, each with a 100k pull-up resistor to 3.3 V. The fifth signal (INT) is active-high and is used to
indicate that data exists in the slave output FIFO. The INT signal does not have a pull-up resistor and
is not driven during initial power-up. The signals are illustrated in
Figure 18
. The SPI slave RX and
TX FIFOs are 4k x 8.
