texet TF-127, Руководство по обслуживанию

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SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM
Rev. 1.2 August 2004
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
Parameter Value Unit
Input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
3.3V
1200
Ω
870
Ω
Output
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Ω
Output
50pF
Z0 = 50
Ω
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
OPERATING AC PARAMETER
Notes :
(AC operating conditions unless otherwise noted)
Parameter Symbol
Version
Unit Note
- 60 (x16 only) - 75
Row active to row active delay t
RRD
(min) 12 15 ns 1
RAS to CAS delay t
RCD
(min) 18 20 ns 1
Row precharge time t
RP
(min) 18 20 ns 1
Row active time
t
RAS
(min) 42 45 ns 1
t
RAS
(max) 100 us
Row cycle time t
RC
(min) 60 65 ns 1
Last data in to row precharge t
RDL
(min) 2 CLK 2,5
Last data in to Active delay t
DAL
(min) 2 CLK + tRP - 5
Last data in to new col. address delay t
CDL
(min) 1 CLK 2
Last data in to burst stop t
BDL
(min) 1 CLK 2
Col. address to col. address delay t
CCD
(min) 1 CLK 3
Number of valid output data
CAS latency=3 2
ea 4
CAS latency=2 - 1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.