AML6210DP A/V Processor User Guide Version 0.2
5/19/2008 7/24
AMLOGIC
Proprietary
3
External Interfaces
3.1
Global Configurations
3.1.1
Power-On Configuration
The chip has a common active-low reset signal called
reset_n
. This signal puts the entire chip into a known
state by resetting internal registers and state-machines to their default states. Typically this signal is held low
for at least 100 msec after the power and crystal clock is stabilized. The reset process also plays a role in
configuring certain functions within the chip. Using the state of the configuration pins and the rising edge of
the
reset_n
signal, the user can dictate the configuration of the JTAG pins and the boot device. The
configuration pins should be pulled up or down using 10K resistors to either 3.3v or ground.
PIN
Function
m1_a_10
This pin controls the JTAG configuration after RESET:
¾
Tie to 3.3v with 10k resistor for JTAG debugging
¾
Tie to ground with a 10k resistor to use the JTAG pins as GPIO
m1_we_n
This pin controls the Boot Option after RESET:
¾
Tie to 3.3v with 10k resistor if the boot device is NAND FLASH
¾
Tie to ground with a 10k resistor if the boot device is NOR FLASH
m1_dqm1
This pin controls the FLASH Data Wide after RESET:
¾
Tie to 3.3v with 10k resistor for 16-bit FLASH device
¾
Tie to ground with a 10k resistor for 8-bit FLASH device
m1_cas_n
This pin controls the NAND Page Size after RESET (only for NAND flash):
¾
Tie to 3.3v with 10k resistor for 512 bytes page size
¾
Tie to ground with a 10k resistor for 2048 bytes page size
m1_ras_n
This pin controls the NAND Flash Size after RESET. The pin controls the number of
ALE pulses that are issued to set the ROW address.
¾
Tie to 3.3v with 10k resistor for large size NAND flash device that needs 3 ALE
pulses
¾
Tie to ground with a 10k resistor for small size NAND device that needs 2 ALE
pulses
Example:
The following example illustrates a start-up configuration for a single 2M Bytes SDRAM and 8-bit FLASH
memory during a production environment (i.e. no JTAG debugging). M1_a_10 is tied to GND to disable JTAG
debugging; m1_we_n is tied to GND to boot from NOR FLASH; and m1_dqm1 is tied to GND for 8-bits NOR
FLASH device.
