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SLLU282A – December 2017 – Revised February 2018
Copyright © 2017–2018, Texas Instruments Incorporated
UCC5390SCD With Isolated Bias Supply
User's Guide
SLLU282A – December 2017 – Revised February 2018
UCC5390SCD With Isolated Bias Supply
This manual describes the UCC5390SCD evaluation module (EVM). The UCC539SCD EVM is designed
to be embedded into a power system by attaching directly to the power FET or IGBT in both TO-220 or
TO-247 packages. This approach helps power system designers verify the performance of the UCC53x0x
drivers and the SN6505B-based bias supply during the early stage of the design in actual system
operating conditions.
WARNING
Although these devices provide galvanic isolation of up to 3000 V,
the EVM cannot be used for isolation voltage testing.
Voltage exceeding the EVM ratings (V
CC1
> 15 V, V
CC2
– V
EE2
> 33 V,
and IGBT collector-emitter voltage V
CE
> 50 V) can damage the
EVM, and result in personal injury.
Contents
1
Introduction
...................................................................................................................
2
General Overview
............................................................................................................
3
Electrical Specifications
.....................................................................................................
4
Detailed Description
.........................................................................................................
5
Test Summary
................................................................................................................
6
Power Up, Capturing Waveforms, and Power Down
..................................................................
7
Bias Supply Performance
.................................................................................................
8
Bill of Materials
.............................................................................................................
9
Layout Diagrams
...........................................................................................................
10
References
..................................................................................................................
List of Figures
1
UCC5390SCDEVM-010 Functional Block Diagram
.....................................................................
2
UCC5390SCDEVM-010 Board Image
....................................................................................
3
UCC5390SCDEVM-010 Electrical Schematic
...........................................................................
4
Soldering UCC5390SCDEVM-010 Board for System Level Evaluation
............................................
5
Test Setup for UCC5390SCDEVM-010 System Level Evaluation
...................................................
6
Gate-Source Driver Voltage
..............................................................................................
7
Expanded Gate-Source Drive Voltage Rise Time
.....................................................................
8
Expanded Gate-Source Drive Voltage Fall Time
......................................................................
9
Inductor Current (Red), Drain-Source (Pink) and Gate-Source Drive Voltages (Blue and Green) at 800-V
Input, 0-A Output
...........................................................................................................
10
Expanded Soft Switching Waveforms During Vds Rise
...............................................................
11
Expanded Soft Switching Waveforms During Vds Fall
................................................................
12
Inductor Current (Red), Drain-Source (Pink) and Gate-Source Drive Voltages (Blue and Green) at 800-V
Input, 1.0-A Output
.........................................................................................................
13
Expanded Hard, 71 V per ns Switching Waveforms During Vds Rise
..............................................
14
Expanded Soft, 3.4 V per ns Switching Waveforms During Vds Fall
...............................................