Texas Instruments TSW1405EVM Скачать руководство пользователя страница 9 | Manualshive

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Texas Instruments TSW1405EVM Скачать руководство пользователя страница 9

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TI TSW1405 High-Speed ADC Evaluation Board

HDL User’s Guide

Table 6. Four Channel Design Signal Names and Pinout

Signal Name

LatticeECP3 Pin

Direction

Definition

reset_n

C21

Input

Master Reset

clk_lvds_rx_p

L4

Input

Clock from TI ADC

clk_lvds_rx_n

M4

Input

TI ADC Channel 1 Data

lvds_rx_port0_p[2]

R3

lvds_rx_port0_n[2]

R2

lvds_rx_port0_p[3]

B2

lvds_rx_port0_n[3]

C2

lvds_rx_port0_p[4]

AA1

lvds_rx_port0_n[4]

Y2

lvds_rx_port0_p[5]

T4

lvds_rx_port0_n[5]

U4

lvds_rx_port0_p[6]

U1

lvds_rx_port0_n[6]

U2

lvds_rx_port0_p[7]

N3

lvds_rx_port0_n[7]

P3

lvds_rx_port0_p[10]

N4

lvds_rx_port0_n[10]

P4

lvds_rx_port0_p[11]

N5

lvds_rx_port0_n[11]

P6

lvds_rx_port0_p[12]

R7

lvds_rx_port0_n[12]

T7

lvds_rx_port0_p[13]

E5

lvds_rx_port0_n[13]

E4

lvds_rx_port0_p[14]

P1

lvds_rx_port0_n[14]

R1

lvds_rx_port0_p[15]

M2

lvds_rx_port0_n[15]

M1

lvds_rx_port1_p[0]

V4

lvds_rx_port1_n[0]

V5

lvds_rx_port1_p[1]

V3

lvds_rx_port1_n[1]

W3

lvds_rx_port1_p[2]

Y3

lvds_rx_port1_n[2]

AA2

lvds_rx_port1_p[3]

W2

lvds_rx_port1_n[3]

Y1

lvds_rx_port1_p[4]

V1

lvds_rx_port1_n[4]

W1

lvds_rx_port1_p[5]

K4

lvds_rx_port1_n[5]

K5

lvds_rx_port1_p[6]

G3

lvds_rx_port1_n[6]

G2

lvds_rx_port1_p[7]

J2

lvds_rx_port1_n[7]

J1

lvds_rx_port1_p[8]

G1

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Содержание TSW1405EVM

Страница 1: ... following TI device families ADS41xx and ADS61xx single channel ADS62Pxx and ADS42xx dual channel ADS58C48 four channel ADS5400 dual bus ADS5463 single channel ADS5485 single channel The HDL reference designs for these converters contain two primary modules for capturing the LVDS data from the ADC ADCIF Contains the I O logic and gearing functions for the LVDS pins It also converts the double dat...

Страница 2: ... sample 1 15 0 15 0 16 16 16 16 16 16 16 16 16 DUMPMEM_DP DUMPMEM_SPI DUMPMEM_WCTRL DUMPMEM_RCTRL spi_miso spi_clk spi_ss reset_n LED ADC Clock Counter TSW1405_2ch_bit_wise DUMPMEM_TOP clk_lvds_rx_p lvds_rx_port0 lvds_rx_port1 17 port1 12 15 9 7 1 16 16 16 16 16 16 16 16 16 16 spi_miso spi_clk i lk spi_ss reset_n LED 13 0 13 0 13 0 13 0 sample 0 chan 0 sample 1 chan 0 sample 0 chan 1 sample 1 chan...

Страница 3: ...MPMEM_WCTRL DUMPMEM_RCTRL spi_miso 28 17 15 10 7 2 cap_chans 16 16 16 16 16 16 16 clk_lvds_rx_p lvds_rx_port0 lvds_rx_port1 spi_clk spi_ss reset_n TSW1405_dual_bus ADCIF DUMPMEM_TOP clk_lvds_rx_p lvds_rx_port0 12 17 sample 0 chan A 16 sample 0 chan B sample 1 chan A sample 1 chan B sample 2 chan A sample 2 chan B sample 3 chan A sample 3 chan B lvds_rx_port1 iDDRx2 DUMPMEM_DP DUMPMEM_SPI DUMPMEM_W...

Страница 4: ...e and dual channel designs TSW1405_sample_wise ADCIF DUMPMEM_TOP clk_lvds_rx_p lvds_rx_port0 lvds_rx_port1 12 17 14 1 IDDRx2 DUMPMEM_DP DUMPMEM_SPI DUMPMEM_WCTRL DUMPMEM_RCTRL spi_miso spi_clk spi_ss reset_n LED ADC Clock Counter 13 0 4 h0 13 0 4 h0 13 0 4 h0 13 0 4 h0 13 0 4 h0 13 0 4 h0 13 0 4 h0 13 0 4 h0 sample 0 sample 0 sample 1 sample 1 sample 2 sample 2 sample 3 sample 3 16 16 16 16 16 16 ...

Страница 5: ...mple 0 Output See Table 2 dout1 1 0 2 b00 See Table 3 dout1 3 0 4 b0000 Chan B Sample 0 Output Sample 0 Output dout1 1 0 2 b00 Sample 0 Output Single data rate output dout2 15 0 Sample 0 Output See Table 2 dout2 1 0 2 b00 See Table 3 dout2 3 0 4 b0000 Chan A Sample 0 Output Sample 0 Output dout2 1 0 2 b00 Sample 0 Output Single data rate output dout3 15 0 Sample 0 Output See Table 2 dout3 1 0 2 b0...

Страница 6: ...e 0 Sample 1 Sample 1 Channel 4 Sample 0 Sample 0 Sample 1 Sample 1 cap_chans 15 Channel 1 Sample 0 Sample 1 Channel 2 Sample 0 Sample 1 Channel 3 Sample 0 Sample 1 Channel 4 Sample 0 Sample 1 cap_chans Setting Channel s dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 cap_chans 0 or 1 Channel 1 Sample 0 Sample 0 Sample 0 Sample 0 Sample 1 Sample 1 Sample 1 Sample 1 cap_chans 2 Channel 2 Sample 0 S...

Страница 7: ...nnel 1 Data lvds_rx_port0_n 4 Y2 lvds_rx_port0_p 5 T4 lvds_rx_port0_n 5 T5 lvds_rx_port0_p 6 U1 lvds_rx_port0_n 6 U2 lvds_rx_port0_p 7 N3 lvds_rx_port0_n 7 P3 lvds_rx_port0_p 9 L3 lvds_rx_port0_n 9 L2 lvds_rx_port0_p 10 N4 lvds_rx_port0_n 10 P4 lvds_rx_port0_p 11 N5 lvds_rx_port0_n 11 P6 lvds_rx_port0_p 12 R7 lvds_rx_port0_n 12 T7 clk_spi A20 Input SPI Clock spi_miso B19 Output SPI Data Out spi_ss...

Страница 8: ...p 4 AA1 lvds_rx_port0_n 4 Y2 lvds_rx_port0_p 5 T4 lvds_rx_port0_n 5 T5 lvds_rx_port0_p 6 U1 lvds_rx_port0_n 6 U2 lvds_rx_port0_p 7 N3 lvds_rx_port0_n 7 P3 lvds_rx_port0_p 9 L3 lvds_rx_port0_n 9 L2 lvds_rx_port0_p 10 N4 lvds_rx_port0_n 10 P4 lvds_rx_port0_p 11 N5 lvds_rx_port0_n 11 P6 lvds_rx_port0_p 12 R7 lvds_rx_port0_n 12 T7 lvds_rx_port0_p 13 E5 lvds_rx_port0_n 13 E4 lvds_rx_port0_p 14 P1 lvds_...

Страница 9: ...x_port0_n 6 U2 lvds_rx_port0_p 7 N3 lvds_rx_port0_n 7 P3 lvds_rx_port0_p 10 N4 lvds_rx_port0_n 10 P4 lvds_rx_port0_p 11 N5 lvds_rx_port0_n 11 P6 lvds_rx_port0_p 12 R7 lvds_rx_port0_n 12 T7 lvds_rx_port0_p 13 E5 lvds_rx_port0_n 13 E4 lvds_rx_port0_p 14 P1 lvds_rx_port0_n 14 R1 lvds_rx_port0_p 15 M2 lvds_rx_port0_n 15 M1 lvds_rx_port1_p 0 V4 lvds_rx_port1_n 0 V5 lvds_rx_port1_p 1 V3 lvds_rx_port1_n ...

Страница 10: ..._rx_p L4 Input Clock from TI ADC clk_lvds_rx_n M4 Input TI ADC Channel 1 Data lvds_rx_port0_p 3 B2 lvds_rx_port0_n 3 C2 lvds_rx_port0_p 4 AA1 lvds_rx_port0_n 4 Y2 lvds_rx_port0_p 5 T4 lvds_rx_port0_n 5 U4 lvds_rx_port0_p 6 U1 lvds_rx_port0_n 6 U2 lvds_rx_port0_p 7 N3 lvds_rx_port0_n 7 P3 lvds_rx_port0_p 10 N4 lvds_rx_port0_n 10 P4 lvds_rx_port0_p 11 N5 lvds_rx_port0_n 11 P6 lvds_rx_port0_p 12 R7 l...

Страница 11: ...port1_p 7 J2 lvds_rx_port1_n 7 J1 lvds_rx_port1_p 8 G1 lvds_rx_port1_n 8 H1 lvds_rx_port1_p 9 E1 lvds_rx_port1_n 9 F1 lvds_rx_port1_p 10 D2 lvds_rx_port1_n 10 D1 lvds_rx_port1_p 11 B1 lvds_rx_port1_n 11 C1 clk_spi A20 Input SPI Clock spi_miso B19 Output SPI Data Out spi_ss B20 Input SPI Source Select LED F19 Output ADC Clock Active Status regbit G18 Output Reserved Table 7 Dual Bus Design Signal N...

Страница 12: ..._n 3 C2 lvds_rx_port0_p 4 AA1 lvds_rx_port0_n 4 Y2 lvds_rx_port0_p 5 T4 lvds_rx_port0_n 5 T5 lvds_rx_port0_p 6 U1 lvds_rx_port0_n 6 U2 lvds_rx_port0_p 7 N3 lvds_rx_port0_n 7 P3 lvds_rx_port0_p 9 L3 lvds_rx_port0_n 9 L2 lvds_rx_port0_p 10 N4 lvds_rx_port0_n 10 P4 lvds_rx_port0_p 11 N5 lvds_rx_port0_n 11 P6 lvds_rx_port0_p 12 R7 lvds_rx_port0_n 12 T7 lvds_rx_port0_p 13 E5 lvds_rx_port0_n 13 E4 lvds_...

Страница 13: ...set to 100 kHz at 4 5Vpp The supply to the ADC board was 5V or 6V depending on the board Signal Name LatticeECP3 Pin Direction Definition reset_n C21 Input Master Reset clk_lvds_rx_p L4 Input Clock from TI ADC clk_lvds_rx_n M4 Input TI ADC Channel 1 Data lvds_rx_port0_p 4 AA1 lvds_rx_port0_n 4 Y2 lvds_rx_port0_p 5 T4 lvds_rx_port0_n 5 T5 lvds_rx_port0_p 6 U1 lvds_rx_port0_n 6 U2 lvds_rx_port0_p 7 ...

Страница 14: ...et Texas Instruments ADS5400 12 Bit 1 GSPS Analog to Digital Converter Data Sheet Texas Instruments ADS5463 12 Bit 500 550 MSPS Analog to Digital Converters Texas Instruments ADS5485 16 Bit 170 200 MSPS Analog to Digital Converters Technical Support Assistance Hotline 1 800 LATTICE North America 1 503 268 8001 Outside North America e mail techsupport latticesemi com Internet www latticesemi com Re...

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