4
TI TSW1405 High-Speed ADC Evaluation Board
HDL User’s Guide
Figure 6. Single Channel ADC Block Diagram (ADS5463)
Figure 7. Single Channel ADC Block Diagram (ADS5485)
The input of the ADCIF module is the single or dual channel double data rate (DDR) output from the ADC. This
input is converted to two single data rate buses for each channel at half the rate of the ADC input clock. The single
channel design is capable of handling up to eight LVDS DDR inputs from the ADC. The dual channel design is
capable of handling up to seven LVDS DDR inputs for the ADC. Table 2 describes the ADCIF I/O for single and dual
channel designs.
TSW1405_sample_wise
ADCIF
DUMPMEM_TOP
clk_lvds_rx_p
lvds_rx_port0
lvds_rx_port1
12
17
[14:1]
IDDRx2
DUMPMEM_DP
DUMPMEM_SPI
DUMPMEM_WCTRL
DUMPMEM_RCTRL
spi_miso
spi_clk
spi_ss
reset_n
LED
ADC Clock Counter
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
sample 0
sample 0
sample 1
sample 1
sample 2
sample 2
sample 3
sample 3
16
16
16
16
16
16
16
16
TSW1405_1ch_edge_bit_wise
ADCIF
DUMPMEM_TOP
clk_lvds_rx_p
lvds_rx_port0
lvds_rx_port1
12
17
{[12:9], [7:4]}
IDDRx2
DUMPMEM_DP
DUMPMEM_SPI
DUMPMEM_WCTRL
DUMPMEM_RCTRL
spi_miso
spi_clk
spi_ss
reset_n
LED
ADC Clock Counter
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
{[13:0], 4’h0}
sample 0
sample 0
sample 1
sample 1
sample 2
sample 2
sample 3
sample 3
16
16
16
16
16
16
16
16
