Texas Instruments TSW1405EVM, Руководство пользователя, Страница: 5 / 14

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TI TSW1405 High-Speed ADC Evaluation Board
HDL User’s Guide
Figure 8. ADCIF Module
Table 1. ADCIF Module NGO I/O Descriptions
ADCIF Signal
TSW1405_1ch_bit_
wise
TSW1405_2ch_bit_
wise
TSW1405_4ch_bit_
wise TSW1405_dual_bus
TSW1405_sample_
wise
TSW1405_1ch_edge
_bit_wise Description
reset_n — — — — — — Design module reset
clk_adc_ext — — — — — — Clock input
inv_data Reserved Reserved Reserved Reserved Reserved Reserved —
inv_clk Reserved Reserved Reserved Reserved Reserved Reserved —
lsb_first Reserved Reserved Reserved Reserved Reserved Reserved —
din[28:0] {din[12:9],din[7:4]} =
Channel 1 input [7:0] din[7:1] =
Channel 1 input din[28:23] =
Channel 1 input din[14:3] =
Channel A input din[14:1] = Channel 1
input {din[12:9],din[7:4]} =
Channel 1 input ADC DDR data input
din[15:9] =
Channel 2 input din[15:10] = Channel 2
input din[28:17] = Channel B
input
din[7:2] =
Channel 3 input
din[22:17] =
Channel 4 input
cap_depth[1:0] Reserved Reserved Reserved Reserved Reserved Reserved —
cap_format[2:0] Reserved Reserved Reserved Reserved Reserved Reserved —
cap_chans[7:0] Reserved 8’d0: Channel 1 – 2
samples/clock 8’d0: Channel 1 – 2
samples/clock Reserved Reserved Reserved
8’d2: Channel 2 – 2
samples/clock 8’d2: Channel 2 – 2
samples/clock Output control mux
8’d3: Dual channel – 4
samples/clock 8’d4: Channel 3 – 2
samples/clock
8’d8: Channel 4 – 2
samples/clock
8'd3: Channels 1 & 2 -
4 samples/clock
8'd12: Channels 3 & 4
- 4 samples/clock
8'd15: Channels 1, 2,
3 & 4 - 8 sam-
ples/clock
clk_adc — — — — — — clk_adc =
clk_adc_ext/2
dout1[15:0] Sample 0 Output See Table 2,
dout1[1:0] = 2’b00 See Table 3,
dout1[3:0] = 4’b0000 Chan B, Sample 0
Output Sample 0 Output,
dout1[1:0] = 2’b00 Sample 0 Output Single data rate output
dout2[15:0] Sample 0 Output See Table 2,
dout2[1:0] = 2’b00 See Table 3,
dout2[3:0] = 4’b0000 Chan A, Sample 0
Output Sample 0 Output,
dout2[1:0] = 2’b00 Sample 0 Output Single data rate output
dout3[15:0] Sample 0 Output See Table 2,
dout3[1:0] = 2’b00 See Table 3,
dout3[3:0] = 4’b0000 Chan B, Sample 1
Output Sample 1 Output,
dout3[1:0] = 2’b00 Sample 0 Outputs Single data rate output
dout4[15:0] Sample 0 Output See Table 2,
dout4[1:0] = 2’b00 See Table 3,
dout4[3:0] = 4’b0000 Chan A, Sample 1
Output Sample 1 Output,
dout4[1:0] = 2’b00 Sample 0 Output Single data rate output
dout5[15:0] Sample 1 Output See Table 2,
dout5[1:0] = 2’b00 See Table 3,
dout5[3:0] = 4’b0000 Chan B, Sample 2
Output Sample 2 Output,
dout5[1:0] = 2’b00 Sample 1 Output Single data rate output
dout6[15:0] Sample 1 Output See Table 2,
dout6[1:0] = 2’b00 See Table 3,
dout6[3:0] = 4’b0000 Chan A, Sample 2
Output Sample 2 Output,
dout6[1:0] = 2’b00 Sample 1 Output Single data rate output
dout7[15:0] Sample 1 Output See Table 2,
dout7[1:0] = 2’b00 See Table 3,
dout7[3:0] = 4’b0000 Chan B, Sample 3
Output Sample 3 Output,
dout7[1:0] = 2’b00 Sample 1 Output Single data rate output
dout8[15:0] Sample 1 Output See Table 2,
dout8[1:0] = 2’b00 See Table 3,
dout8[3:0] = 4’b0000 Chan A, Sample 3
Output Sample 3 Output,
dout8[1:0] = 2’b00 Sample 1 Output Single data rate output
clk_adc
dout1[15:0]
dout2[15:0]
dout3[15:0]
dout4[15:0]
dout5[15:0]
dout6[15:0]
dout7[15:0]
dout8[15:0]
clk_adc_ext
ADCIF
inv_data
inv_clk
lsb_first
reset_n
din[28:0]
cap_depth[1:0]
cap_format[2:0]
cap_chans[7:0]