8
TI TSW1405 High-Speed ADC Evaluation Board
HDL User’s Guide
Table 5. Dual Channel Design Signal Names and Pinout
Signal Name
LatticeECP3 Pin
Direction
Definition
reset_n
C21
Input
Master Reset
clk_lvds_rx_p
L4
Input
Clock from TI ADC
clk_lvds_rx_n
M4
Input
TI ADC Channel 1 Data
lvds_rx_port0_p[1]
R4
lvds_rx_port0_n[1]
T5
lvds_rx_port0_p[2]
R3
lvds_rx_port0_n[2]
R2
lvds_rx_port0_p[3]
B2
lvds_rx_port0_n[3]
C2
lvds_rx_port0_p[4]
AA1
lvds_rx_port0_n[4]
Y2
lvds_rx_port0_p[5]
T4
lvds_rx_port0_n[5]
T5
lvds_rx_port0_p[6]
U1
lvds_rx_port0_n[6]
U2
lvds_rx_port0_p[7]
N3
lvds_rx_port0_n[7]
P3
lvds_rx_port0_p[9]
L3
lvds_rx_port0_n[9]
L2
lvds_rx_port0_p[10]
N4
lvds_rx_port0_n[10]
P4
lvds_rx_port0_p[11]
N5
lvds_rx_port0_n[11]
P6
lvds_rx_port0_p[12]
R7
lvds_rx_port0_n[12]
T7
lvds_rx_port0_p[13]
E5
lvds_rx_port0_n[13]
E4
lvds_rx_port0_p[14]
P1
lvds_rx_port0_n[14]
R1
lvds_rx_port0_p[15]
M2
lvds_rx_port0_n[15]
M1
clk_spi
A20
Input
SPI Clock
spi_miso
B19
Output
SPI Data Out
spi_ss
B20
Input
SPI Source Select
LED
F19
Output
ADC Clock Active Status
regbit
G18
Output
Reserved
