3
TI TSW1405 High-Speed ADC Evaluation Board
HDL User’s Guide
Figure 4. Four Channel ADC Block Diagram (ADS58C48)
Figure 5. Dual Bus ADC Block Diagram (ADS5400)
TSW1405_2ch_bit_wise
ADCIF
DUMPMEM_TOP
17
12
sample 0, chan 0
16
sample 1, chan 0
sample 0, chan 1
sample 1, chan 1
sample 0, chan 2
sample 1, chan 2
sample 0, chan 3
[11:0]
[11:0]
[11:0]
[11:0]
[11:0]
[11:0]
[11:0]
iDDRx2
DUMPMEM_DP
DUMPMEM_SPI
DUMPMEM_WCTRL
DUMPMEM_RCTRL
spi_miso
{[28:17], [15:10], [7:2]}
cap_chans
16
16
16
16
16
16
16
clk_lvds_rx_p
lvds_rx_port0
lvds_rx_port1
spi_clk
spi_ss
reset_n
TSW1405_dual_bus
ADCIF
DUMPMEM_TOP
clk_lvds_rx_p
lvds_rx_port0
12
17
sample 0, chan A
16
sample 0, chan B
sample 1, chan A
sample 1, chan B
sample 2, chan A
sample 2, chan B
sample 3, chan A
sample 3, chan B
lvds_rx_port1
iDDRx2
DUMPMEM_DP
DUMPMEM_SPI
DUMPMEM_WCTRL
DUMPMEM_RCTRL
spi_miso
LED
spi_clk
spi_ss
reset_n
16
16
16
16
16
16
16
ADC Clock Counter
{[11:0], h’40}
{[28:17],
[14:3]}
{[11:0], h’40}
{[11:0], h’40}
{[11:0], h’40}
{[11:0], h’40}
{[11:0], h’40}
{[11:0], h’40}
{[11:0], h’40}