Texas Instruments TMS320TCI648 Series, Руководство пользователя

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Registers
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6 Registers
The VCP2 contains several memory-mapped registers accessible by the CPU, the IDMA, the QDMA, and
the EDMA3. A configuration-bus access is faster than an EDMA3-bus access for isolated accesses
(typically when accessing control registers). EDMA3-bus accesses are used for EDMA3 transfers and
provide maximum throughput to/from the VCP2. The registers are listed in
Table 5 . For the memory map
and full register addresses, see the device-specific data manual.
The branch metric and traceback decision memories contents are not accessible and the memories can
be regarded as FIFOs by the DSP, meaning you do not have to perform any indexing on the addresses.
Table 5. VCP2 Registers
EDMA3 Bus Configuration Bus
Offsets Offsets Acronym Register Name See
0000h VCPPID VCP peripheral ID register Section 6.1
0000h VCPIC0 VCP input configuration register 0 Section 6.2
0004h VCPIC1 VCP input configuration register 1 Section 6.3
0008h VCPIC2 VCP input configuration register 2 Section 6.4
000Ch VCPIC3 VCP input configuration register 3 Section 6.5
0010h VCPIC4 VCP input configuration register 4 Section 6.6
0014h VCPIC5 VCP input configuration register 5 Section 6.7
0048h VCPOUT0 VCP output register 0 Section 6.8
004Ch VCPOUT1 VCP output register 1 Section 6.9
0080h VCPWBM VCP branch metrics write FIFO register
00C0h VCPRDECS VCP decisions read FIFO register
0018h VCPEXE VCP execution register Section 6.10
0020h VCPEND VCP endian mode register Section 6.11
0040h VCPSTAT0 VCP status register 0 Section 6.12
0044h VCPSTAT1 VCP status register 1 Section 6.13
0050h VCPERR VCP error register Section 6.14
0060h VCPEMU VCP emulation control register Section 6.15
Table 6. VCP2 Memories
EDMA3 Bus Offsets Acronym Name Size
1000h BM Branch Metrics (BM) 256 Bytes
2000h SM State Metric (SM) 448 Bytes
3000h TBHD Traceback Hard Decision 4K Bytes
6000h TBSD Traceback Soft Decision 16K Bytes
F000h IO Decoded Bits (IO) 512 Bytes
NOTE: Register and Memory Access
• Data Transfer Alignment: Normal (non-emulation) mode data transfers to/from the VCP2
must be aligned on a double-word (64-bit) boundary. Alignment can be forced in C using
the 'DATA_ALIGN' pragma. Non-alignment results in data transfer failure.
Example:
#pragma DATA_ALIGN(configIc, 8) // Should be double-word aligned
VCP_ConfigIc configIc; // VCP Input Configuration Reg
• Data Transfer Size: Normal (non-emulation) mode data transfers to/from the VCP2 must
be of a length that is an 8-byte (double-word) multiple.
• Emulation mode transfers are performed on 32-bit boundaries and are 4 bytes in length.
14 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009
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