Texas Instruments TMS320TCI648 Series, Руководство пользователя

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Registers
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6.12 VCP2 Status Register 0 (VCPSTAT0)
The VCP2 status register 0 (VCPSTAT0) is shown in Figure 15 and described in Table 18 .
Figure 15. VCP2 Status Register 0 (VCPSTAT0)
31 29 28 16
Reserved NSYMPROC
R/W-0 R-0
15 12 11 8
NSYMPROC Reserved
R-0 R/W-0
7 6 5 4 3 2 1 0
EMU
Reserved OFFUL IFEMP WIC ERR RUN PAUSE
HALT
R/W-0 R-0 R-0 R-1 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. VCP2 Status Register 0 (VCPSTAT0) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
28-12 NSYMPROC Number of symbols processed bits. The NSYMPROC bits indicate how many symbols have been
processed in the state metric unit with respect to time.
The maximum number of processed stages is equal to f + (k-1) in tailed or mixed mode. The
maximum number of processed stages is equal to f + c in convergent mode.
11-7 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
6 EMUHALT Emulation halt status bit.
0 No halt due to emulation.
1 Halt due to emulation.
5 OFFUL Output FIFO buffer full status bit.
0 Output FIFO buffer is not full.
1 Output FIFO buffer is full.
4 IFEMP Input FIFO buffer empty status bit.
0 Input FIFO buffer is not empty.
1 Input FIFO buffer is empty.
3 WIC Waiting for input configuration bit. The WIC bit indicates that the VCP is waiting for new input
control parameters to be written. This bit is always set after decoding of a user channel.
0 Not waiting for input configuration words.
1 Waiting for input configuration words.
2 ERR VCP error status bit. The ERR bit is cleared as soon as the DSP reads the VCP error register
(VCPERR).
0 No error.
1 VCP paused due to error.
1 RUN VCP running status bit.
0 VCP is not running.
1 VCP is running.
0 PAUSE VCP pause status bit.
0 VCP is not paused. The UNPAUSE command is acknowledged by clearing the PAUSE bit.
1 VCP is paused. The PAUSE command is acknowledged by setting the PAUSE bit. The PAUSE bit
can also be set, if the input FIFO buffer is becoming empty or if the output FIFO buffer is full.
26 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009
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