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Registers

6.7

VCP2 Input Configuration Register 5 (VCPIC5)

The VCP2 input configuration register 5 (VCPIC5) is shown in

Figure 10

and described in

Table 13

Figure 10. VCP2 Input Configuration Register 5 (VCPIC5)

SDHD

OUTF

Reserved

SYMR

SYMX

R/W-0

Reserved

IMAXI

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. VCP2 Input Configuration Register 5 (VCPIC5) Field Descriptions

Bit

Field

Value

Description

SDHD

Output decision type select bit.

Hard decisions

Soft decisions

OUTF

Output parameters read flag bit.

VCPREVT is not generated by VCP for output parameters read

VCPREVT generated by VCP for output parameters read

29-28

Traceback mode select bits.

Not allowed

Tailed, F

≤

max

(1)

Convergent, (no tail bits)

Mixed, F

≥

max

and tail bits are used

27-25

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

24-20

SYMR

0-1Fh

Determines decision buffer length in output FIFO. For information on selecting the appropriate
SYMR value, see

Section 8.4

19-16

SYMX

0-Fh

Determines branch metrics buffer length in input FIFO. For information on selecting the appropriate
SYMX value, see

Section 8.3

15-8

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

7-0

IMAXI

0-FFh

Maximum initial state metric value bits. IMAXI bits determine which state should be initialized with
the maximum state metrics value (IMAXS) bits in VCPIC4; all the other states are initialized with the
value in the IMINS bits.

(1)

For more details on F

max

, see

Section 8.1.4

SPRUE09E – May 2006 – Revised December 2009

TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2

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Содержание TMS320TCI648 Series

Страница 1: ...TMS320TCI648x 9x DSP Viterbi Decoder Coprocessor 2 VCP2 User s Guide Literature Number SPRUE09E May 2006 Revised December 2009...

Страница 3: ...Register VCPEXE 24 6 11 VCP2 Endian Mode Register VCPEND 25 6 12 VCP2 Status Register 0 VCPSTAT0 26 6 13 VCP2 Status Register 1 VCPSTAT1 27 6 14 VCP2 Error Register VCPERR 28 6 15 VCP2 Emulation Contr...

Страница 4: ...25 15 VCP2 Status Register 0 VCPSTAT0 26 16 VCP2 Status Register 1 VCPSTAT1 27 17 VCP2 Error Register VCPERR 28 18 VCP2 Emulation Control Register VCPEMU 30 19 Data Source VBUSP DMA BM 1 31 20 Data De...

Страница 5: ...ld Descriptions 22 15 VCP2 Output Register 1 VCPOUT1 Field Descriptions 23 16 VCP2 Execution Register VCPEXE Field Descriptions 24 17 VCP2 Endian Mode Register VCPEND Field Descriptions 25 18 VCP2 Sta...

Страница 6: ...ion The term word describes a 32 bit value Related Documentation From Texas Instruments The following documents describe the C6000 devices and related support tools Copies of these documents are avail...

Страница 7: ...333 MHz 1 Features The VCP2 provides High flexibility Variable constraint length K 5 6 7 8 or 9 User supplied code coefficients Code rates 1 2 1 3 or 1 4 Configurable trace back settings convergence...

Страница 8: ...eful representation of the code but whose complexity grows exponentially with the constraint length K Figure 2 shows the trellis diagram of the code from Figure 1 The fact that there is a limited numb...

Страница 9: ...ncoder Example NOTE K 3 R k n 1 3 G0 100 8 G1 101 8 G2 111 8 0 000 means input is 0 output1 is 0 output2 is 0 output3 is 0 There are 2 K 1 states and 2k incoming branches per state 9 SPRUE09E May 2006...

Страница 10: ...typically sends and receives data using synchronized EDMA3 transfers through the EDMA3 bus The VCP2 sends two synchronization events to the EDMA3 a receive event VCPREVT and a transmit event VCPXEVT T...

Страница 11: ...re 1 Rate 1 4 there are 8 branch metrics per symbol period BM0 t r0 t r1 t r2 t r3 t BM1 t r0 t r1 t r2 t r3 t BM2 t r0 t r1 t r2 t r3 t BM3 t r0 t r1 t r2 t r3 t BM4 t r0 t r1 t r2 t r3 t BM5 t r0 t...

Страница 12: ...oss of decoding performance The VCP2 is designed with C 13 The branch metrics can have a maximum dynamic range of 7 1 sign bits 128 127 This gives another branch metrics upper bound B 2 128 So for a g...

Страница 13: ...s see the VCP2 endian mode register Section 6 3 The decisions buffer start address must be double word aligned and the buffer size must be a multiple of 8 bytes The soft decisions in the VCP2 are init...

Страница 14: ...egister 1 Section 6 9 0080h VCPWBM VCP branch metrics write FIFO register 00C0h VCPRDECS VCP decisions read FIFO register 0018h VCPEXE VCP execution register Section 6 10 0020h VCPEND VCP endian mode...

Страница 15: ...MINOR R 1 R 0 R 0x80A R rtl R major R R minor custom LEGEND R W Read Write R Read only n value after reset Table 7 VCP2 Peripheral ID Register VCPPID Field Descriptions Bit Field Value Description TCI...

Страница 16: ...9 2 7 0 POLY0 0 FFh Polynomial generator G0 see Section 9 2 1 The polynomial generators are 9 bit values defined as G z b8z 8 b7z 7 b6z 6 b5z 5 b4z 4 b3z 3 b2z 2 b1z 1 b0 but only 8 bits are passed i...

Страница 17: ...s Bit Field Value Description 31 29 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 28 YAMEN Yamamoto algorithm enable bit See Section 8 2...

Страница 18: ...nfiguration Register 2 VCPIC2 Field Descriptions Bit Field Value Description 31 16 R 0 FFFFh Reliability length bits see Section 8 1 15 0 FL 0 FFFFh Frame length bits see Section 8 1 The total number...

Страница 19: ...ct 28 OUT_ORDER 0 and 1 Defines the order of VCP output for decoded data 0 0 to 31 1 31 to 0 27 25 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has n...

Страница 20: ...egister 4 VCPIC4 Field Descriptions Bit Field Value Description 31 29 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 28 16 IMINS 0 1FFFh...

Страница 21: ...o tail bits 3h Mixed F Fmax and tail bits are used 27 25 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 24 20 SYMR 0 1Fh Determines decis...

Страница 22: ...alue Description 31 29 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 28 16 FMINS 0 FFFh Minimum final state metric value 13 bits 15 13 R...

Страница 23: ...it and is only used if the Yamamoto logic is enabled See Section 8 2 0 At least one trellis stage had an absolute difference less than the Yamamoto threshold and the decided frame has poor quality 1 N...

Страница 24: ...sing the state metric for the current sliding window and before the start of the traceback 3h Restart VCP and process one sliding window debug mode The VCP is restarted from the pause state and begins...

Страница 25: ...et Table 17 VCP2 Endian Mode Register VCPEND Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no...

Страница 26: ...6 EMUHALT Emulation halt status bit 0 No halt due to emulation 1 Halt due to emulation 5 OFFUL Output FIFO buffer full status bit 0 Output FIFO buffer is not full 1 Output FIFO buffer is full 4 IFEMP...

Страница 27: ...ead Write R Read only n value after reset Table 19 VCP2 Status Register 1 VCPSTAT1 Field Descriptions Bit Field Value Description 31 16 NSYMOF 0 FFFFh Number of symbols in the output FIFO buffer 15 0...

Страница 28: ...48 Soft 31 32 f 2048 Soft 15 16 f 2048 1 Error occurred 5 E_SYMX 0 No error for SMAX as shown in the following relationships Code Rate SYMX of 64 Bit Transfers of BM per trellis per 1 4 3 16 128 16 1...

Страница 29: ...tions continued Bit Field Value Description 0 ERROR 0 No error is detected 1 An error has occurred 29 SPRUE09E May 2006 Revised December 2009 TMS320TCI648x 9x Viterbi Decoder Coprocessor 2 Submit Docu...

Страница 30: ...after reset Table 21 VCP2 Emulation Control Register VCPEMU Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to th...

Страница 31: ...0 1 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 bytes 1 0 Endianness manager has no effect 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 bytes 1 1 Endianness manager has no effect 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 bytes Table 2...

Страница 32: ...BMs as shown in Figure 22 for processing Figure 21 Data Source VBUSP DMA BM 0 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 BM3 BM2 BM1 BM0 BM7 BM7 BM5 BM4 Figure 22 Data Destination Kernel for Proces...

Страница 33: ...DER 1 63 62 32 31 1 0 Stage Stage Stage Stage Stage Stage N 31 N 30 N N 63 N 33 N 32 7 1 2 Soft Decisions The VCP2 soft decisions are 8 bit results and output 64 bits at a time The soft decisions are...

Страница 34: ...2 K 1 symbols The traceback soft decision memory can store up to 8192 traceback soft values and therefore contain up to 8192 soft decisions of 8192 2 K 1 symbols Assume a terminated frame of length F...

Страница 35: ...one in parallel with the traceback computation of sliding window I Tailed traceback type is used on the last sliding window 8 1 3 Convergent Traceback Mode This mode is used with non terminated frames...

Страница 36: ...accumulation which is largely unaffected by the choice of R and C Hard decisions R C max for mixed convergent processing for hard decisions has been increased from 605 to 635 for K 6 and from 1020 to...

Страница 37: ...to accept new data The value of SYMX in the VCPIC5 register determines the number of 64 bit transfers of input data expected to be written into the input FIFO by the EDMA for each VCPXEVT event Table...

Страница 38: ...for hard decision output or F 256 for soft decision output and SYMR is calculated as shown a single VCPREVT event is generated once all the output data has been written to the output FIFO 38 TMS320TCI...

Страница 39: ...3 channel 28 is primarily intended to serve VCP2 to DSP transfers Event 29 is associated to the VCP2 transmit event VCPXEVT and is used as the synchronization event for EDMA3 transfers from the DSP to...

Страница 40: ...he EDMA3 for branch metrics transfer parameters 9 1 2 2 Branch Metrics Transfer This EDMA3 transfer to the branch metrics FIFO is a VCPXEVT frame synchronized transfer The OPTIONS should be set as ITC...

Страница 41: ...n this EDMA3 transfer is linked to one of the following 1 The decisions EDMA3 transfer parameters of the next user channel if there is one ready to be decoded and the OUTF bit is 0 2 Null EDMA3 transf...

Страница 42: ...RCBIDX 0 DSTBIDX ACNT SRCCIDX 0 DSTCIDX 0 CCNT 1 Number of frames in a block 9 1 2 6 Output Parameters Transfer This transfer is optional and depends on the OUTF bit It is a 2 to 32 bit word VCPREVT f...

Страница 43: ...CPIC1 are described in Section 8 2 The F and R bits in VCPIC2 the C bit in VCPIC3 and the TB bits in VCPIC5 are described in Section 8 1 The IMAXI bits in VCPIC5 determine which state should be initia...

Страница 44: ...of input configurations then a dummy transfer should be set up to avoid an SER event flag being set for the EDMA3 parameter entry If the flag is set it effectively locks the VCP2 and must be cleared b...

Страница 45: ...s are used and the internal VCP2 memories can be inspected at various points in the decoding process The procedure for using this command is as follows VCP2 configuration and branch metrics are prepar...

Страница 46: ...set up interrupts see the TMS320C6000 DSP Interrupt Selector Reference Guide SPRU646 The status registers are provided for debugging purposes and are best used when either the processor is halted or t...

Страница 47: ...Table 30 TCI648x 9x Revision History See Additions Modifications Deletions Table 10 Modified bits 15 0 FL description Section 8 1 4 Modified step 4 in numbered list Modified last paragraph 47 SPRUE09...

Страница 48: ...ce TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonabl...

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