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Architecture
8.2
Yamamoto Parameters
During the standard forward recursion, an entity called the Yamamoto bit is computed for each state and
updated every symbol interval. The Yamamoto bit was proposed by Hirosuke Yamamoto (Hirosuke
Yamamoto, Viterbi Decoding Algorithm for Convolutional Codes with Repeat Request, IEEE Transactions
on Information Theory, Vol. IT-26, No. 5, September 1980).
Basically, a bit (the Yamamoto bit) is associated with each state in the decoding process. Initially, all the
Yamamoto bits are set (1). During the decoding process, the Yamamoto bit for a particular state comes
from a couple of decisions made on the path metrics and the Yamamoto bit of previous states. The
metrics of all paths leading to a particular state are compared. If the difference between any two metrics is
less than a given threshold (YAMT bits in VCPIC1), then the Yamamoto bit is cleared; otherwise, the
Yamamoto bit is inherited from the previous state of the path with the largest metric. The end result of this
process (YAM bit in VCPOUT1) yields a zero (0) if anywhere along the decoding path there was a point
where the decision between two paths was ambiguous. The YAM bit can therefore be used as a binary
frame quality indicator.
The Yamamoto algorithm can be enabled or disabled by toggling the YAMEN bit in VCPIC1.
8.3
Input FIFO (Branch Metrics)
The branch metric input FIFO uses a double-buffering scheme to allow the transfer of new input data while
processing the current data. After the VCP2 is initiated, it generates a VCPXEVT EDMA synchronization
event each time one side of the input FIFO is empty (and, thus, ready to accept new data). The value of
SYMX in the VCPIC5 register determines the number of 64-bit transfers of input data expected to be
written into the input FIFO by the EDMA for each VCPXEVT event.
lists the valid values for SYMX, along with the corresponding number of expected 64-bit
transfers. As shown for the supported code rates, the VCP2 can be programmed to expect either 8 or 16
64-bit transfers for each VCPXEVT event.
The VCP2 only generates as many VCPXEVT events as needed to transfer all the branch metric input
data required for the current code block. In other words, no excess VCPXEVT events are generated
based on the FIFO being empty at the end of processing.
Table 28. Code Rate versus SYMX
Code Rate
SYMX
Number of 64-Bit Transfers
1/4
3
16
1/4
1
8
1/3
7
16
1/3
3
8
1/2
15
16
1/2
7
8
8.4
Output FIFO (Decisions)
The decoded decision output FIFO uses a double-buffering scheme to allow the EDMA to transfer out
available decoded data while the VCP2 processes and writes more decoded data. The VCP2 generates a
VCPREVT EDMA synchronization event each time one side of the output FIFO is full. In the case that all
the decoded data fits within one side of the output FIFO, only one VCPREVT is generated after all the
data has been written to the FIFO.
The value of SYMR in the VCPIC5 register should be set to one less than the number of 64-bit transfers
of output data expected to be transferred from the output FIFO by the EDMA for each VCPREVT event.
The possible range for SYMR is 1 to 31. SYMR should be calculated as follows:
•
For hard decisions:
–
If F
≤
2048, then SYMR = ceil (F/64) - 1
–
If F > 2048, then SYMR = 15 or 31
•
For soft decisions:
37
SPRUE09E – May 2006 – Revised December 2009
TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2
Copyright © 2006–2009, Texas Instruments Incorporated