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Registers
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6.10 VCP2 Execution Register (VCPEXE)
The VCP2 execution register (VCPEXE) is shown in Figure 13 and described in Table 16 .
Figure 13. VCP2 Execution Register (VCPEXE)
31 4 3 0
Reserved COMMAND
R/W-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. VCP2 Execution Register (VCPEXE) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
3-0 COMMAND VCP command select bits; see Section 10 .
0 Reserved (no instruction)
1h Start VCP (normal mode)
2h Halt or Pause VCP (debug mode). The VCP is halted (or paused) after processing the state
metric for the current sliding window and before the start of the traceback.
3h Restart VCP and process one sliding window (debug mode). The VCP is restarted from the
pause state and begins the traceback operation. The VCP is again paused after processing
the state metrics for next sliding window.
4h Restart VCP (debug mode). The VCP is restarted from the paused state and begins the
traceback operation. The VCP will run to normal completion.
5h Stop. Soft reset all VCP registers to their initial condition. All registers in the VCP are reset in
this mode except for the execution register, endian register, emulation register, and other
internal registers.
6h-FFh Reserved
24 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009
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