Texas Instruments TMS320TCI648 Series, Руководство пользователя

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Registers
6.3 VCP2 Input Configuration Register 1 (VCPIC1)
The VCP2 input configuration register 1 (VCPIC1) is shown in Figure 6 and described in Table 9 .
Figure 6. VCP2 Input Configuration Register 1 (VCPIC1)
31 29 28 27 16
Reserved YAMEN YAMT
R/W-0 R/W-0 R/W-0
15 0
Reserved
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. VCP2 Input Configuration Register 1 (VCPIC1) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
28 YAMEN Yamamoto algorithm enable bit. See Section 8.2 .
0 Yamamoto algorithm is disabled.
1 Yamamoto algorithm is enabled.
27-16 YAMT 0-FFFh Yamamoto threshold value bits. See Section 8.2 .
15-0 Reserved 0 Reserved. These reserved bit locations must be 0. A value written to this field has no effect.
17 SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2
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