www.ti.com
Programming
For convergent mode, Total number of Branch Metrics = (F + C) × (2
(r
−
1)
)
•
DESTINATION ADDRESS: VCPWBM branch metrics FIFO address
•
SRCBIDX = ACNT
•
DSTBIDX = 0
•
SRCCIDX = 0
•
DSTCIDX = 0
•
CCNT = 1 (Number of frames in a block)
Upon completion, this EDMA3 transfer is linked to one of the following:
•
The DMA input configuration parameters transfer parameters of the next user channel, if there is one
ready to be decoded.
•
Dummy DMA transfer parameters, if there are no more user channels ready to be decoded [for
information on how to set up a dummy Xfer, see the TMS320C6472/TMS320TCI648x DSP Enhanced
DMA (EDMA3) Controller User's Guide (
)]. Do not link to a NULL transfer, as the secondary
event register will set the event flag for Event 29. The final VCPXEVT is generated upon the reading of
the decisions and output registers, which is intended to transfer the input configuration of the next user
channel. If a NULL transfer link is in place, the final VCPXEVT will set the event 29 flag of SER and no
further VCP execution will occur until it is cleared.
9.1.2.3
Decisions Transfer
EDMA3 transfers from the decision buffer are VCPREVT frame-synchronized transfers. The programming
of these transfers depend on the decision type and the traceback mode.
Upon completion, this EDMA3 transfer is linked to one of the following:
1. The decisions EDMA3 transfer parameters of the next user channel, if there is one ready to be
decoded and the OUTF bit is 0.
2. Null EDMA3 transfer parameters (with all zeros), if there are no more user channels ready to be
decoded and the OUTF bit is 0.
3. The output parameters EDMA3 transfer parameters, if the OUTF bit is 1.
9.1.2.4
Hard-Decisions Mode
The OPTIONS should be set as:
•
ITCCEN = 0 (Intermediate transfer complete chaining is disabled)
•
TCCEN = 0 (Transfer complete chaining is disabled)
•
ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)
•
TCINTEN = 0 (Transfer complete interrupt is disabled)
•
WIMODE = 0 (Normal operation)
•
TCC = 1 to 63 (Transfer complete code)
•
TCCMODE = 0 (Normal completion)
•
FWID = Don't care
•
STAT = 0 (Entry is updated as normal)
•
SYNCDIM = 0 (A-sync transfer, each event triggers the transfer of ACNT elements)
•
DAM = 0 (Dst address within an array increments. Dst is not a FIFO.)
•
SAM = 1 (Src Address is fixed. Src is a FIFO.)
•
SOURCE ADDRESS: VCPRDECS Decision FIFO address
•
ACNT = (SYMR+1) × 8 (Number of hard decision bytes in an array)
•
BCNT = CEIL(TNHD/ACNT) (Number of arrays in a frame) Where TNHD is the total number of hard
decisions in bytes (Framelength/8).
•
Destination Address: hard-decision array address
•
SRCBIDX = 0
•
DSTBIDX = ACNT
•
SRCCIDX = 0
41
SPRUE09E – May 2006 – Revised December 2009
TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2
Copyright © 2006–2009, Texas Instruments Incorporated
