Programmable Gain Amplifier Gain Control
1-6
General Information
1.3
Programmable Gain Amplifier Gain Control
The THS7001 IC is provided with three digital control inputs for setting the gain
of the PGA stage (G0 – G2). Standard TTL or CMOS Logic signals operate
these control inputs. The gain control inputs are not latched and respond to the
control signals in real time. Therefore, the control signals on these inputs must
remain constant if the PGA gain is to remain constant. For stand-alone
evaluation of this function, onboard DIP switches (S1:A to S1:C) are used to
control the gain of the PGA. Note that all DIP switch gain control elements must
be set to OFF if gain is to be set by digital control signals. For convenience,
test points (TP2 – TP4) are placed on each of these lines to allow easy external
connections. There are 330-
Ω
isolation resistors in series with each IC gain
control input pins. These were added only for surge suppression and are not
required for actual system design. Nominal gain/attenuation is shown in
Table 1–1.
Table 1–1. THS7001 EVM PGA Nominal Gain/Attenuation
G2
G1
G0
PGA Gain (dB)
PGA Gain (V/V)
0
0
0
–22
0.08
0
0
1
–16
0.16
0
1
0
–10
0.32
0
1
1
–4
0.63
1
0
0
2
1.26
1
0
1
8
2.52
1
1
0
14
5.01
1
1
1
20
10
One aspect of the THS7001 PGA signal input that must be considered is that
there are internal variable resistors (R
F
and R
G
) that set the gain. The
resistance of R
G
changes from about 270
Ω
(gain = +20 dB) to about 3 k
Ω
(gain
= –22 dB). Therefore, any source impedance at the input to the PGA amplifier
will cause a gain error to be seen at the output. A buffer/amplifier is highly
recommended to directly drive the input of the PGA section to help minimize
this effect.
Another consideration is that when the amplifier V
REF
is connected to ground,
the internal R
G
resistor is connected to a virtual ground. Therefore, if a
termination resistor is used on the source side, the total terminating resistance
is the parallel combination of the terminating resistance and the internal R
G
resistor. This, in conjunction with the series impedance problem mentioned
previously, can potentially cause a voltage mismatch between the output of a
50-
Ω
source and the expected PGA output voltage.
These points are illustrated by the following formula and in the simplified
diagram of the THS7001 PGA section shown in Figure 1–3.
R
TOTALTERMINATION
+
R
TERMINATION
(R
SOURCE
)
R
G
)
R
TERMINATION
)
(R
SOURCE
)
R
G
)
(3)
