42
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
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MSP430G2203
Detailed Description
Copyright © 2011–2016, Texas Instruments Incorporated
6.8
Flash Memory
The flash memory can be programmed through the Spy-Bi-Wire/JTAG port or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory
include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
•
Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are
also called
information memory
.
•
Segment A contains calibration data. After reset segment A is protected against programming and
erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific
calibration data is required.
6.9
Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the
MSP430x2xx Family User's
Guide
(
SLAU144
).
6.9.1
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch
crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled
oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost
and low power consumption. The internal DCO provides a fast turnon clock source and stabilizes in less
than 1 µs. The basic clock module provides the following clock signals:
•
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
•
Main clock (MCLK), the system clock used by the CPU.
•
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
